changeset 3b0bcc8c34ca in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3b0bcc8c34ca
description:
ruby: slicc: change enqueue statement
As of now, the enqueue statement can take in any number of 'pairs' as
argument. But we only use the pair in which latency is the key. This
latency is allowed to be either a fixed integer or a member variable of
controller in which the expression appears. This patch drops the use
of pairs
in an enqueue statement. Instead, an expression is allowed which will
be
interpreted to be the latency of the enqueue. This expression can
anything
allowed by slicc including a constant integer or a member variable.
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 12 ++--
src/mem/protocol/MESI_Three_Level-L1cache.sm | 36 ++++++------
src/mem/protocol/MESI_Two_Level-L1cache.sm | 41 ++++++-------
src/mem/protocol/MESI_Two_Level-L2cache.sm | 32 +++++-----
src/mem/protocol/MESI_Two_Level-dir.sm | 24 ++++----
src/mem/protocol/MESI_Two_Level-dma.sm | 4 +-
src/mem/protocol/MI_example-cache.sm | 8 +-
src/mem/protocol/MI_example-dir.sm | 28 ++++----
src/mem/protocol/MI_example-dma.sm | 4 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 43 ++++++-------
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 74 ++++++++++++------------
src/mem/protocol/MOESI_CMP_directory-dir.sm | 24 ++++----
src/mem/protocol/MOESI_CMP_directory-dma.sm | 6 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 46 +++++++-------
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 46 +++++++--------
src/mem/protocol/MOESI_CMP_token-dir.sm | 44 +++++++-------
src/mem/protocol/MOESI_CMP_token-dma.sm | 4 +-
src/mem/protocol/MOESI_hammer-cache.sm | 48 ++++++++--------
src/mem/protocol/MOESI_hammer-dir.sm | 52 ++++++++--------
src/mem/protocol/MOESI_hammer-dma.sm | 4 +-
src/mem/protocol/Network_test-cache.sm | 6 +-
src/mem/slicc/ast/EnqueueStatementAST.py | 26 +++-----
src/mem/slicc/parser.py | 24 ++++---
23 files changed, 310 insertions(+), 326 deletions(-)
diffs (truncated from 2754 to 300 lines):
diff -r 525b7e432f76 -r 3b0bcc8c34ca
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Tue Apr 08 13:26:29
2014 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Tue Apr 08 13:26:30
2014 -0500
@@ -350,7 +350,7 @@
// ACTIONS
action(a_issueGETS, "a", desc="Issue GETS") {
peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestNetwork_out, CoherenceMsg, latency=request_latency) {
+ enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
out_msg.Addr := address;
out_msg.Class := CoherenceClass:GETS;
out_msg.Sender := machineID;
@@ -365,7 +365,7 @@
action(b_issueGETX, "b", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestNetwork_out, CoherenceMsg, latency=request_latency) {
+ enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
out_msg.Addr := address;
out_msg.Class := CoherenceClass:GETX;
out_msg.Sender := machineID;
@@ -382,7 +382,7 @@
action(c_issueUPGRADE, "c", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestNetwork_out, CoherenceMsg, latency= request_latency) {
+ enqueue(requestNetwork_out, CoherenceMsg, request_latency) {
out_msg.Addr := address;
out_msg.Class := CoherenceClass:UPGRADE;
out_msg.Sender := machineID;
@@ -397,7 +397,7 @@
}
action(f_sendDataToL1, "f", desc="send data to the L2 cache") {
- enqueue(requestNetwork_out, CoherenceMsg, latency=response_latency) {
+ enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Class := CoherenceClass:INV_DATA;
@@ -411,7 +411,7 @@
action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
peek(messgeBuffer_in, CoherenceMsg) {
- enqueue(requestNetwork_out, CoherenceMsg, latency=response_latency) {
+ enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
out_msg.Addr := address;
out_msg.Class := CoherenceClass:INV_ACK;
out_msg.Sender := machineID;
@@ -429,7 +429,7 @@
}
action(g_issuePUTX, "g", desc="send data to the L2 cache") {
- enqueue(requestNetwork_out, CoherenceMsg, latency=response_latency) {
+ enqueue(requestNetwork_out, CoherenceMsg, response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Class := CoherenceClass:PUTX;
diff -r 525b7e432f76 -r 3b0bcc8c34ca
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Tue Apr 08 13:26:29
2014 -0500
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Tue Apr 08 13:26:30
2014 -0500
@@ -370,7 +370,7 @@
// ACTIONS
action(a_issueGETS, "a", desc="Issue GETS") {
peek(messageBufferFromL0_in, CoherenceMsg) {
- enqueue(requestNetwork_out, RequestMsg, latency=l1_request_latency) {
+ enqueue(requestNetwork_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
@@ -386,7 +386,7 @@
action(b_issueGETX, "b", desc="Issue GETX") {
peek(messageBufferFromL0_in, CoherenceMsg) {
- enqueue(requestNetwork_out, RequestMsg, latency=l1_request_latency) {
+ enqueue(requestNetwork_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
@@ -403,7 +403,7 @@
action(c_issueUPGRADE, "c", desc="Issue GETX") {
peek(messageBufferFromL0_in, CoherenceMsg) {
- enqueue(requestNetwork_out, RequestMsg, latency= l1_request_latency) {
+ enqueue(requestNetwork_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:UPGRADE;
out_msg.Requestor := machineID;
@@ -419,7 +419,7 @@
action(d_sendDataToRequestor, "d", desc="send data to requestor") {
peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -433,7 +433,7 @@
}
action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M
downgrade") {
- enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -448,7 +448,7 @@
action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") {
peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(tbe));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -462,7 +462,7 @@
}
action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
- enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(tbe));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -477,7 +477,7 @@
action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor
(could be L2 or L1)") {
peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
@@ -488,7 +488,7 @@
}
action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
- enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -502,7 +502,7 @@
}
action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
- enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
assert(is_valid(tbe));
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:DATA;
@@ -517,7 +517,7 @@
action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=l1_response_latency) {
+ enqueue(responseNetwork_out, ResponseMsg, l1_response_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:ACK;
out_msg.Sender := machineID;
@@ -529,7 +529,7 @@
}
action(forward_eviction_to_L0, "\cc", desc="sends eviction information to
the processor") {
- enqueue(bufferToL0_out, CoherenceMsg, latency=l1_request_latency) {
+ enqueue(bufferToL0_out, CoherenceMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Class := CoherenceClass:INV;
out_msg.Sender := machineID;
@@ -539,7 +539,7 @@
}
action(g_issuePUTX, "g", desc="send data to the L2 cache") {
- enqueue(requestNetwork_out, RequestMsg, latency=l1_response_latency) {
+ enqueue(requestNetwork_out, RequestMsg, l1_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:PUTX;
@@ -557,7 +557,7 @@
}
action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
- enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
+ enqueue(unblockNetwork_out, ResponseMsg, to_l2_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:UNBLOCK;
out_msg.Sender := machineID;
@@ -569,7 +569,7 @@
}
action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
- enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
+ enqueue(unblockNetwork_out, ResponseMsg, to_l2_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
out_msg.Sender := machineID;
@@ -582,7 +582,7 @@
}
action(h_data_to_l0, "h", desc="If not prefetch, send data to the L0
cache.") {
- enqueue(bufferToL0_out, CoherenceMsg, latency=l1_response_latency) {
+ enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
@@ -596,7 +596,7 @@
}
action(h_stale_data_to_l0, "hs", desc="If not prefetch, send data to the L0
cache.") {
- enqueue(bufferToL0_out, CoherenceMsg, latency=l1_response_latency) {
+ enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
@@ -610,7 +610,7 @@
}
action(hh_xdata_to_l0, "\h", desc="If not prefetch, notify sequencer that
store completed.") {
- enqueue(bufferToL0_out, CoherenceMsg, latency=l1_response_latency) {
+ enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) {
assert(is_valid(cache_entry));
out_msg.Addr := address;
diff -r 525b7e432f76 -r 3b0bcc8c34ca src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Tue Apr 08 13:26:29
2014 -0500
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Tue Apr 08 13:26:30
2014 -0500
@@ -485,7 +485,7 @@
}
void enqueuePrefetch(Address address, RubyRequestType type) {
- enqueue(optionalQueue_out, RubyRequest, latency=1) {
+ enqueue(optionalQueue_out, RubyRequest, 1) {
out_msg.LineAddress := address;
out_msg.Type := type;
out_msg.AccessMode := RubyAccessMode:Supervisor;
@@ -495,7 +495,7 @@
// ACTIONS
action(a_issueGETS, "a", desc="Issue GETS") {
peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) {
+ enqueue(requestL1Network_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
@@ -512,8 +512,7 @@
action(pa_issuePfGETS, "pa", desc="Issue prefetch GETS") {
peek(optionalQueue_in, RubyRequest) {
- enqueue(requestL1Network_out, RequestMsg,
- latency=l1_request_latency) {
+ enqueue(requestL1Network_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
@@ -530,7 +529,7 @@
action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) {
+ enqueue(requestL1Network_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GET_INSTR;
out_msg.Requestor := machineID;
@@ -548,8 +547,7 @@
action(pai_issuePfGETINSTR, "pai",
desc="Issue GETINSTR for prefetch request") {
peek(optionalQueue_in, RubyRequest) {
- enqueue(requestL1Network_out, RequestMsg,
- latency=l1_request_latency) {
+ enqueue(requestL1Network_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GET_INSTR;
out_msg.Requestor := machineID;
@@ -568,7 +566,7 @@
action(b_issueGETX, "b", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestL1Network_out, RequestMsg, latency=l1_request_latency) {
+ enqueue(requestL1Network_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
@@ -586,8 +584,7 @@
action(pb_issuePfGETX, "pb", desc="Issue prefetch GETX") {
peek(optionalQueue_in, RubyRequest) {
- enqueue(requestL1Network_out, RequestMsg,
- latency=l1_request_latency) {
+ enqueue(requestL1Network_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:GETX;
out_msg.Requestor := machineID;
@@ -607,7 +604,7 @@
action(c_issueUPGRADE, "c", desc="Issue GETX") {
peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestL1Network_out, RequestMsg, latency= l1_request_latency) {
+ enqueue(requestL1Network_out, RequestMsg, l1_request_latency) {
out_msg.Addr := address;
out_msg.Type := CoherenceRequestType:UPGRADE;
out_msg.Requestor := machineID;
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
