changeset e475a7861078 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=e475a7861078 description: sparc: Fixup bit ordering in the PSTATE bit union
The order of the MSB and LSB bit of the mm field in the PSTATE union is wrong. Any access to this field will currently be ignored and reads will always return zero. This patch fixes the ordering so it is <MSB, LSB> instead of <LSB, MSB>. diffstat: src/arch/sparc/miscregs.hh | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diffs (12 lines): diff -r 4966471a1ba1 -r e475a7861078 src/arch/sparc/miscregs.hh --- a/src/arch/sparc/miscregs.hh Tue Aug 26 10:13:03 2014 -0400 +++ b/src/arch/sparc/miscregs.hh Tue Aug 26 10:13:23 2014 -0400 @@ -129,7 +129,7 @@ Bitfield<2> priv; Bitfield<3> am; Bitfield<4> pef; - Bitfield<6, 7> mm; + Bitfield<7, 6> mm; Bitfield<8> tle; Bitfield<9> cle; Bitfield<10> pid0; _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev