changeset ffec48040ac1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ffec48040ac1
description:
tests: Always specify memory mode in every test system.
Previous to this change we didn't always set the memory mode which
worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs
verify
that they're operating in the correct mode and thus we need to always
set it.
diffstat:
tests/configs/inorder-timing.py | 3 ++-
tests/configs/o3-timing-checker.py | 3 ++-
tests/configs/o3-timing-mp-ruby.py | 3 ++-
tests/configs/o3-timing-mp.py | 5 ++++-
tests/configs/o3-timing-ruby.py | 3 ++-
tests/configs/o3-timing.py | 3 ++-
tests/configs/simple-timing.py | 3 ++-
7 files changed, 16 insertions(+), 7 deletions(-)
diffs (93 lines):
diff -r e428871da248 -r ffec48040ac1 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py Mon Jan 07 13:05:33 2013 -0500
+++ b/tests/configs/inorder-timing.py Mon Jan 07 13:05:33 2013 -0500
@@ -40,7 +40,8 @@
system = System(cpu = cpu,
physmem = SimpleDRAM(),
- membus = CoherentBus())
+ membus = CoherentBus(),
+ mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
diff -r e428871da248 -r ffec48040ac1 tests/configs/o3-timing-checker.py
--- a/tests/configs/o3-timing-checker.py Mon Jan 07 13:05:33 2013 -0500
+++ b/tests/configs/o3-timing-checker.py Mon Jan 07 13:05:33 2013 -0500
@@ -53,7 +53,8 @@
system = System(cpu = cpu,
physmem = SimpleDRAM(),
- membus = CoherentBus())
+ membus = CoherentBus(),
+ mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
cpu.connectAllPorts(system.membus)
diff -r e428871da248 -r ffec48040ac1 tests/configs/o3-timing-mp-ruby.py
--- a/tests/configs/o3-timing-mp-ruby.py Mon Jan 07 13:05:33 2013 -0500
+++ b/tests/configs/o3-timing-mp-ruby.py Mon Jan 07 13:05:33 2013 -0500
@@ -38,7 +38,8 @@
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
+ mem_mode = "timing")
for cpu in cpus:
# create the interrupt controller
diff -r e428871da248 -r ffec48040ac1 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Mon Jan 07 13:05:33 2013 -0500
+++ b/tests/configs/o3-timing-mp.py Mon Jan 07 13:05:33 2013 -0500
@@ -35,7 +35,10 @@
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
-system = System(cpu = cpus, physmem = SimpleDRAM(), membus = CoherentBus())
+system = System(cpu = cpus,
+ physmem = SimpleDRAM(),
+ membus = CoherentBus(),
+ mem_mode = "timing")
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')
diff -r e428871da248 -r ffec48040ac1 tests/configs/o3-timing-ruby.py
--- a/tests/configs/o3-timing-ruby.py Mon Jan 07 13:05:33 2013 -0500
+++ b/tests/configs/o3-timing-ruby.py Mon Jan 07 13:05:33 2013 -0500
@@ -40,7 +40,8 @@
system = System(cpu = cpu,
physmem = ruby_memory,
- membus = CoherentBus())
+ membus = CoherentBus(),
+ mem_mode = "timing")
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
diff -r e428871da248 -r ffec48040ac1 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Mon Jan 07 13:05:33 2013 -0500
+++ b/tests/configs/o3-timing.py Mon Jan 07 13:05:33 2013 -0500
@@ -42,7 +42,8 @@
system = System(cpu = cpu,
physmem = SimpleDRAM(),
- membus = CoherentBus())
+ membus = CoherentBus(),
+ mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
diff -r e428871da248 -r ffec48040ac1 tests/configs/simple-timing.py
--- a/tests/configs/simple-timing.py Mon Jan 07 13:05:33 2013 -0500
+++ b/tests/configs/simple-timing.py Mon Jan 07 13:05:33 2013 -0500
@@ -37,7 +37,8 @@
L2Cache(size = '2MB'))
system = System(cpu = cpu,
physmem = SimpleMemory(),
- membus = CoherentBus())
+ membus = CoherentBus(),
+ mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller
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