changeset af63ab37f87c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=af63ab37f87c
description:
i8254xGBe: major style overhaul.
Moved DescCache template functions from .hh to .cc file.
Also fixed lots of line-wrapping problems, and some irregular
indent
changeset 9af6fb59752f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=9af6fb59752f
description:
mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. No
changeset 82c377317a86 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=82c377317a86
description:
Update stats for new single bad-address responder.
Mostly just config.ini updates, though the different response
latency for bad addresses caused very minor ti
On Tue, Apr 21, 2009 at 6:26 PM, Korey Sewell wrote:
>
> That's not what I mean. What I'm saying is, simulate the timing of a
>> TLB stage, but do the functional access with the memory stage. I.e.
>> split it for timing purposes, but leave it together for functional
>> reasons. I'd be surprise
I couldn't deal with it right away and then forgot about it. It's still
broken to the best of my knowledge.
Gabe
nathan binkert wrote:
> Whatever happened with this? I just lost track.
>
> Nate
>
>
>> It's broader than tracing and not caused by the tracing mechanism
>> itself, but I think i
> That's not what I mean. What I'm saying is, simulate the timing of a
> TLB stage, but do the functional access with the memory stage. I.e.
> split it for timing purposes, but leave it together for functional
> reasons. I'd be surprised if this does not work since the timing of
> TLB accesses a
Whatever happened with this? I just lost track.
Nate
> It's broader than tracing and not caused by the tracing mechanism
> itself, but I think it will only show up with tracing. The pointer to
> the trace data will be NULL otherwise and the instruction won't
> attempt to use it. Nothing else t
>> I'll admit that I'm not following this thread very closely, but the
>> biggest question I have is: is it necessary to actually do the
>> translation in the translation pipe stage?
>>
>> Can't it just be there to
>> burn a cycle while you do the actual translation when executing the
>> read?
>
>
changeset 18aff7f548c1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=18aff7f548c1
description:
scons: Rename the basic environment from env -> main.
env is used as a local variable all over the place and sometimes it is
easy to get confused as to whethe
changeset 4dcea6c903fa in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4dcea6c903fa
description:
scons: Fix two problems with the way that the library path is generated.
1) -L is automatically added, so don't do it ourselves
2) prepend the paths for gzstre
changeset aeb2cf497240 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aeb2cf497240
description:
Automated merge with ssh://m5sim.org//repo/m5
diffstat:
6 files changed, 66 insertions(+), 131 deletions(-)
src/arch/arm/ArmTLB.py| 19
src/arch/arm/microc
changeset bcf332c99e40 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bcf332c99e40
description:
arm: include missing file for arm
diffstat:
1 file changed, 41 insertions(+)
src/arch/arm/microcode_rom.hh | 41 +
diffs (45 lines)
changeset a1d388751779 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a1d388751779
description:
pseudo: only include kernel stats if FULL_SYSTEM.
diffstat:
1 file changed, 4 insertions(+), 1 deletion(-)
src/sim/pseudo_inst.cc |5 -
diffs (23 lines):
diff -r bc
changeset a5a97b04d796 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a5a97b04d796
description:
arm: Unify the ARM tlb. We forgot about this when we did the rest.
This code compiles, but there are no tests still
diffstat:
4 files changed, 21 insertions(+), 130
> Another question for Korey though is what if you want to model a virtually
> indexed physically tagged cache where the cache and TLB accesses are
> concurrent? In that case it might not be easy to guarantee that translate()
> is called before read() or write().
That's a good point. I think sinc
OK, I took a week off from the InOrder stuff to fix MIPS-O3, so I'm getting
back to this...BTW, I got the gzip regression to pass earlier today
w/Inorder so we're on our way hopefully from that standpoint...
To refresh our memory, we were discussing how to get the size of a memory
access and the f
changeset 83e66a2e06ee in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=83e66a2e06ee
description:
FastAlloc: track allocation tick in debug mode,
minor enhancements to debug output
diffstat:
2 files changed, 55 insertions(+), 10 deletions(-)
src/base/fast_alloc.
changeset 7c6971582cd4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7c6971582cd4
description:
rundiff: flush stdout after each diff
diffstat:
1 file changed, 3 insertions(+), 1 deletion(-)
util/rundiff |4 +++-
diffs (21 lines):
diff -r 83e66a2e06ee -r 7c6971582
changeset 4e008e4ecc92 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4e008e4ecc92
description:
scons: make default target work again
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
SConstruct |2 +-
diffs (12 lines):
diff -r 21f6eaab12df -r 4e008e4ecc92 S
I agree with Nate... I think deducing the logical system configuration
directly from an arbitrary M5 SimObject tree is going to be next to
impossible, given that the tree doesn't reflect the memory hierarchy
interconnection topology, and since the M5 tree could very easily correspond
to an undescri
changeset 21f6eaab12df in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=21f6eaab12df
description:
Set up m5threads tests on classic (non-ruby) memory system.
Just one test (40.m5threads-test-atomic) is set up for now.
These tests require that the m5threads
changeset 5666d4eb6bbd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5666d4eb6bbd
description:
syscall_emul: style fixes (mostly wrapping overly long lines)
diffstat:
1 file changed, 28 insertions(+), 20 deletions(-)
src/sim/syscall_emul.cc | 48
changeset 5051aafec8d5 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5051aafec8d5
description:
syscall: Resolve conflicts between m5threads and Gabe's recent SE
changes.
diffstat:
9 files changed, 13 insertions(+), 14 deletions(-)
src/arch/alpha/isa_traits.hh |1
changeset 083d8a76b7a6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=083d8a76b7a6
description:
Commit m5threads package.
This patch adds limited multithreading support in syscall-emulation
mode, by using the clone system call. The clone system call wor
changeset d41da05de9ad in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d41da05de9ad
description:
request: add PREFETCH flag.
diffstat:
1 file changed, 3 insertions(+)
src/mem/request.hh |3 +++
diffs (20 lines):
diff -r a27c0934de24 -r d41da05de9ad src/mem/request.
changeset 52a5e1c63380 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=52a5e1c63380
description:
Minor tweaks for future Ruby compatibility.
diffstat:
2 files changed, 4 insertions(+), 4 deletions(-)
configs/common/Simulation.py |6 ++
src/mem/physical.hh
changeset a27c0934de24 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a27c0934de24
description:
request: rename INST_READ to INST_FETCH.
diffstat:
6 files changed, 14 insertions(+), 13 deletions(-)
src/cpu/ozone/inorder_back_end.hh |8
src/cpu/simple/base.
changeset 66014cd0dc61 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=66014cd0dc61
description:
SCons: Export export_vars so SConsopts files can add to them
diffstat:
2 files changed, 9 insertions(+), 6 deletions(-)
SConstruct | 11 +++
src/SConscript |
changeset ca0915f8d86d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ca0915f8d86d
description:
request: split public and private flags into separate fields.
This frees up needed space for more public flags. Also:
- remove unused Request accessor methods
It seems reasonable, although I'm sure it will be easier said than done
one you get down to the details. The challenge will be putting it
together so that it doesn't make so many assumptions that it becomes
useless outside of traditional sorts of configurations like, for
instance, meshes. I agree t
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