changeset aac74ffc8ca2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=aac74ffc8ca2
description:
isa_parser: Get rid of the now unused ControlBitfieldOperand.
diffstat:
1 file changed, 26 deletions(-)
src/arch/isa_parser.py | 26 --
diffs (36 l
changeset eaf61ef6a8f2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=eaf61ef6a8f2
description:
MIPS: Use BitUnions instead of bits() functions and constants.
Also fix style issues in regions around these changes.
diffstat:
8 files changed, 920 insertions(+), 1
Yes.
On Mon, Jul 20, 2009 at 5:46 PM, Lisa Hsu wrote:
> anyone get this?
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anyone get this?
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Hi Derek,
Has Nate mentioned his cprintf package to you? It's basically a
type-safe C++ printf, which most of us find much nicer than C++ stream
I/O, particularly if you have to do a lot of formatting. I don't
consider it a major integration issue (like integrating statistics or
debugging), but
changeset 74f0cd03dfa2 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=74f0cd03dfa2
description:
merge
diffstat:
15 files changed, 588 insertions(+), 292 deletions(-)
src/arch/sparc/SConscript |3
src/arch/sparc/SparcNativeTrace.py | 35 ++
src/arch/sp
changeset 11423b4639c0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=11423b4639c0
description:
ruby: moved cache stats from Profiler to CacheMemory
Caches are now responsible for their own statistic gathering. This
requires a direct callback from the p
changeset 544d4ee1 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=544d4ee1
description:
scons: removed RubyConfig from scons
diffstat:
1 file changed, 1 deletion(-)
src/mem/ruby/config/SConscript |1 -
diffs (8 lines):
diff -r f1a41ea3bbab -r 544d4ee1
changeset f1a41ea3bbab in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=f1a41ea3bbab
description:
ruby: removed all refs to old RubyConfig
diffstat:
45 files changed, 30 insertions(+), 1211 deletions(-)
src/mem/ruby/buffers/MessageBuffer.cc |
changeset a1768b396928 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a1768b396928
description:
ruby: removed dead files
diffstat:
1 file changed, 82 deletions(-)
src/mem/ruby/network/simple/PtToPtTopology.cc | 82 -
diffs (86 lines):
diff -r
changeset 82ac95f4d9f0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=82ac95f4d9f0
description:
merge
diffstat:
60 files changed, 1727 insertions(+), 1231 deletions(-)
src/arch/arm/linux/linux.hh
| 46 +-
src/a
changeset ebfc37fa8615 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ebfc37fa8615
description:
ruby: removed dead files
diffstat:
1 file changed, 45 deletions(-)
src/mem/ruby/system/ProcessorInterface.hh | 45 -
diffs (49 lines):
diff -r
changeset cecc7019b458 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=cecc7019b458
description:
ruby: fixed dma sequencer bug
The DMASequencer was still using a parameter from the old RubyConfig,
causing an offset error when the requested data wasn't blo
changeset c6254810bb6c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c6254810bb6c
description:
slicc: made coherence profilers per-controller
diffstat:
1 file changed, 11 insertions(+), 6 deletions(-)
src/mem/slicc/symbols/StateMachine.cc | 17 +++--
dif
changeset c4e91b8e3da3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c4e91b8e3da3
description:
ruby: better debug print for DataBlock
diffstat:
1 file changed, 2 insertions(+), 2 deletions(-)
src/mem/ruby/common/DataBlock.hh |4 ++--
diffs (14 lines):
diff -r c62
No big deal, but we decided a while ago that if you have accessors, it
should be:
int _foo;
int foo() const { return _foo; }
void foo(int val) { _foo = val; }
instead of:
int foo;
int getFoo() const { return foo; }
void setFoo(int val) { foo = val; }
On Mon, Jul 20, 2
changeset a3037fa327a0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a3037fa327a0
description:
CPU: Separate out native trace into ISA (in)dependent code and
SimObjects.
diffstat:
12 files changed, 554 insertions(+), 291 deletions(-)
src/arch/sparc/SConscript
changeset a8c27fe8b28a in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a8c27fe8b28a
description:
X86: Add some misc registers for FP control state.
diffstat:
1 file changed, 11 insertions(+)
src/arch/x86/miscregs.hh | 11 +++
diffs (21 lines):
diff -r 62de7e7
changeset a17979b4e1ea in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a17979b4e1ea
description:
X86: Move a displaced comment back to where it goes.
diffstat:
1 file changed, 1 insertion(+), 1 deletion(-)
src/arch/x86/process.cc |2 +-
diffs (19 lines):
diff -r a8
changeset a71fd8e252b7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=a71fd8e252b7
description:
Tracing: Add accessors so tracers can get at data in trace records.
diffstat:
1 file changed, 22 insertions(+)
src/sim/insttracer.hh | 22 ++
diffs (32
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