My build of kernel version 2.6.28.4 now works as well as 2.6.22.9, or in
other words gets through the kernel boot fine and segfaults in an init
script some place. There's a big annoying warning at the beginning about
mtrrs not being set up, but the kernel silences that warning if it can
tell it's r
changeset 92c3973dd98c in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=92c3973dd98c
description:
IDE: Configure the IDE control to reflect the initial value of the
command register.
diffstat:
1 file changed, 3 insertions(+)
src/dev/ide_ctrl.cc |3 +++
diffs (13 lin
changeset 550f76603d41 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=550f76603d41
description:
X86: Set up the IDE device correctly, ie. with and using legacy ports.
diffstat:
1 file changed, 2 insertions(+), 1 deletion(-)
src/dev/x86/SouthBridge.py |3 ++-
diffs
On Sun, Aug 2, 2009 at 1:17 PM, nathan binkert wrote:
>> Also, I think with this flag in place we ought to be able to get rid
>> of the tlb_mode setting; the TLB can just look and see whether
>> isInstFetch() is true to decide how to handle the request... does
>> anyone agree or disagree?
>
> Well,
Fine with me... one thing to clarify though is whether in the long run:
A. all class members should start with underscore just in case we want
to give them accessors later
or
B. only class members with accessors should start with underscore, and
others don't
I prefer B, mostly because A would b
What I did for either SPARC or x86 (or both?) was that I made that
function templated on a type instead of taking intSize. Then you can
call it with however large a type you need and it should work out.
You'll also probably want separate MIPS32 and MIPS64 process objects
since syscalls may be diff
Hey Gabe,
the point of interest in the code is here:
> +//
> +// NOTE: Using uint32_t hardcodes MIPS32 and not MIPS64
> +// even if MIPS64 was intended. This is because the
> +// copyStringArray function templates on the parameters.
> +// Elegant way to check intSize an
> Also, I think with this flag in place we ought to be able to get rid
> of the tlb_mode setting; the TLB can just look and see whether
> isInstFetch() is true to decide how to handle the request... does
> anyone agree or disagree?
Well, mode is read/write/execute. You're proposing figuring just
Very awesome. I was tempted to do this a number of times. I'm going
to go ahead and add this standard to the style guide. ok?
Nate
On Sat, Aug 1, 2009 at 10:51 PM, Steve Reinhardt wrote:
> changeset 50125d42559c in /z/repo/m5
> details: http://repo.m5sim.org/m5?cmd=changeset;node=50125d42559
Along these lines, I do think figuring out how to consolidate process
start up code more would be a good idea. SPARC and x86 are to the best
of my knowledge byte identical to the machine I was using when I worked
on them, and ARM is byte identical to a slightly newer kernel. They're
almost ISA inde
I'm confused... Where's Addr in this code? Why can't you just substitute
a different type if it's templated?
Korey Sewell wrote:
> # HG changeset patch
> # User Korey Sewell
> # Date 1249236222 14400
> # Node ID 5aa846b0397fa026286ab54fa29a9d87cca4f932
> # Parent e46754b929cab9cf21a3f4d8578ae580
# HG changeset patch
# User Korey Sewell
# Date 1249236222 14400
# Node ID 5aa846b0397fa026286ab54fa29a9d87cca4f932
# Parent e46754b929cab9cf21a3f4d8578ae58071a526fd
mips_se_args: fix for MIPS32 command line arguments
In the base argsInit function, command line args were being processed by a
te
changeset 4c5671ecceda in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=4c5671ecceda
description:
X86: Fix the high result of mul1s, and removed undefined shifts from
the mult microops.
diffstat:
1 file changed, 19 insertions(+), 15 deletions(-)
src/arch/x86/isa/microop
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed.
* build/ALPHA_SE/tests/fast/quick/30.eio-mp/al
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