On Sun, Nov 15, 2009 at 4:27 PM, Gabe Black wrote:
> This sort of question should be on the m5sim-users mailing list. Please
> move it there.
>
> Agreed, but if he wants to actually dig into the code and fix it/submit a
patch should it go on m5-dev? its a little ambiguous what to do there...
-
This sort of question should be on the m5sim-users mailing list. Please
move it there.
Gabe
Sujay Phadke wrote:
> Hello,
> I am trying to use M5-dev (latest) in SE mode with multiple cpu's
> (n=4) switching from atomic->timing->detailed. However, the assertion
> in src/cpu/o3/thread_context_
Hello,
I am trying to use M5-dev (latest) in SE mode with multiple cpu's (n=4)
switching from atomic->timing->detailed. However, the assertion in
src/cpu/o3/thread_context_impl.hh takeOverFrom() fails.
getSystemPtr() == old_context->getSystemPtr()
This takeOverFrom() is called from src/cpu/o3
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed.
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
passed.
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed.
* build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/
changeset 72836109775f in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=72836109775f
description:
ARM: Create a new type of load uop that restores spsr into cpsr.
diffstat:
1 file changed, 17 insertions(+)
src/arch/arm/isa/formats/macromem.isa | 17 +
d
changeset e9970c1bccdd in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e9970c1bccdd
description:
ARM: Make the exception return form of ldm restore CPSR.
diffstat:
1 file changed, 10 insertions(+), 3 deletions(-)
src/arch/arm/isa/formats/macromem.isa | 13 ++--
