Re: [m5-dev] Patches for SMARTS simulation

> 7) Made various bug fixes and alterations to correct corner cases I found > when implementing this stuff. > > I'm not so sure about 1) and it would be good to get Kevin's input on that. > I hope to extend it to make one generic branch predictor so that the > in-order core can make use of it too,

[m5-dev] Patches for SMARTS simulation

Hi everyone, I've just posted to the review board 12 patches that enable me to perform SMARTS-like sampling simulation. Most are finished and I'd be happy to commit them if everyone is ok with them. A couple are not quite there yet and I'd like input on whether they are correct and whether

[m5-dev] Review Request: Sim: Add functionality to the simulation scripts to allow running with

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/57/ --- Review request for Default. Summary --- Sim: Add functionality to the simulatio

[m5-dev] Review Request: Stats: Allow backing up and restoring of stats which is needed for SMARTS

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/56/ --- Review request for Default. Summary --- Stats: Allow backing up and restoring o

[m5-dev] Review Request: Port: Only indicate that a SimpleTimingPort is drained if its send event is

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/55/ --- Review request for Default. Summary --- Port: Only indicate that a SimpleTiming

[m5-dev] Review Request: O3CPU: Fix a bug where stores in the cpu where never marked as split.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/54/ --- Review request for Default. Summary --- O3CPU: Fix a bug where stores in the cp

[m5-dev] Review Request: Cache: Provide a function to mark caches as ready from python.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/53/ --- Review request for Default. Summary --- Cache: Provide a function to mark cache

[m5-dev] Review Request: Syscall: Don't close the simulator's standard file descriptors.

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/52/ --- Review request for Default. Summary --- Syscall: Don't close the simulator's st

[m5-dev] Review Request: CPU: Add functions to get the number of executed instructions and set the

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/51/ --- Review request for Default. Summary --- CPU: Add functions to get the number of

[m5-dev] Review Request: O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/50/ --- Review request for Default. Summary --- O3CPU: O3's tick event gets squashed wh

[m5-dev] Review Request: Sim: When one CPU is taking over from another, the new CPU's memory is only

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/49/ --- Review request for Default. Summary --- Sim: When one CPU is taking over from a

[m5-dev] Review Request: SimpleCPU: Allow Simple CPUs to warm a branch predictor by creating a pointer

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/48/ --- Review request for Default. Summary --- SimpleCPU: Allow Simple CPUs to warm a

[m5-dev] Review Request: BranchPred: Take the branch predictor out of O3CPU and make it a stand-alone

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/47/ --- Review request for Default. Summary --- BranchPred: Take the branch predictor o

Re: [m5-dev] how to use m5threads?

Hi Eberle, Yes I compiled with the –static flag. gcc -ggdb3 -O3 -D__DEBUG -c ../pthread.c -o ../pthread.o g++ -g -O3 –D__DEBUG -c -o test_pthreadbasic.o test_pthreadbasic.cpp g++ -static -o test_pthreadbasic test_pthreadbasic.o ../pthread.o is what the Makefile in m5threads/test does by defaul

Re: [m5-dev] how to use m5threads?

Hi Tushar, yes, something like that happened to me. You compiled (linked) with the -static flag, right? -- Eberle A. Rambo. On Fri, Jul 9, 2010 at 9:30 PM, Krishna, Tushar wrote: > Thanks Eberle. > > I did a make on the tests within m5threads using my system's regular > gcc/g++ (for x86), and

[m5-dev] Review Request: Power: Provide a utility function to copy registers from one thread context

--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/35/ --- Review request for Default. Summary --- Power: Provide a utility function to co

Re: [m5-dev] how to use m5threads?

Thanks Eberle. I did a make on the tests within m5threads using my system's regular gcc/g++ (for x86), and tried running one of the binaries through M5 in X86_SE mode like this: ./build/X86_SE/m5.debug configs/example/se.py --cmd=m5threads/tests/test_pthreadsbasic I get the following error: Gl

Re: [m5-dev] a question on CPU assertions

On Fri, Jul 9, 2010 at 5:41 PM, Min Kyu Jeong wrote: > The following is the excerpt from the disassembly. > > 117c: e321f013 msr CPSR_c, #19 ; 0x13 > 1180: e24fd08c sub sp, pc, #140 ; 0x8c > 1184: e321f011 msr CPSR_c, #17 ; 0x11 > 1188: e24fd094 sub sp, pc, #148 ; 0x94 > 118c:

Re: [m5-dev] a question on CPU assertions

The following is the excerpt from the disassembly. 117c: e321f013 msr CPSR_c, #19 ; 0x13 1180: e24fd08c sub sp, pc, #140 ; 0x8c 1184: e321f011 msr CPSR_c, #17 ; 0x11 1188: e24fd094 sub sp, pc, #148 ; 0x94 118c: e321f012 msr CPSR_c, #18 ; 0x12 1190: e24fd09c sub sp, pc, #156

Re: [m5-dev] a question on CPU assertions

Thanks for the extra info which should be very helpful. Can you please tell us what the actual bytes are for the junk instruction? Gabe Quoting Min Kyu Jeong : I looked into this thing, but still don't fully understand how the out-of-bound reg index causes segfault. Instead, I will just desc

Re: [m5-dev] a question on CPU assertions

I looked into this thing, but still don't fully understand how the out-of-bound reg index causes segfault. Instead, I will just describe what is happening hoping someone would catch a clue from it. The register index that goes out of bound is the architectural register index, stored in StaticInst

[m5-dev] Reviewboard password

Hi all, Can anyone tell me how to retrieve my password for the review board? I've just accidentally logged out and can't find any sort of 'Forgotten password' link or anything of that kind. My user name is tmjones, if that helps. Cheers Tim -- Timothy M. Jones http://homepages.inf.ed.