On Tue, Jul 13, 2010 at 5:47 PM, Gabriel Michael Black
gbl...@eecs.umich.edu wrote:
Quoting Steve Reinhardt ste...@gmail.com:
On Tue, Jul 13, 2010 at 11:20 AM, Gabe Black gbl...@eecs.umich.edu
wrote:
I can't say it was -the- reason, but one reason is that the TLBs as is
don't actually send
Here, try this patch.
Gabe
Gabriel Michael Black wrote:
That one I think should be fixed in the decoder. If the mode isn't
valid, an Uknown(machInst) should be returned rather than the Srs
instruction. I'll try to get the previous patch cleaned up and
committed and a patch for this to you
Thank you all for the suggestions!
=== I have the following questions: ===
1. how would M5 support plugins with pseudo instructions in the ISA?
Following Gabe's thoughts:
* M5 can provide general, customizable pseudo instructions
One possibility is to have this pseudo instruction
It looks like the right place to place the code that checks for a fault and
calls the CPU read/write function would be
BaseDynInstImpl::finishTranslation().
All the code to make this work seems to be there already. If it hits in the
TLB, then TheISA::TLB::translateTiming() should call
Hi Pritha,
The warnings you mentioned are expected and can be ignored as long as they only
complain about Ruby Sim Objects. The reason for them is the checkpoint you
created using normal ALPHA FS, only checkpointed the Sim Objects used by normal
ALPHA FS, but when a Ruby enabled system loads
