changeset be7c22eb8c20 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=be7c22eb8c20
description:
ARM: Make an SRS instruction with a bad mode cause an undefined
instruction fault.
diffstat:
src/arch/arm/isa/formats/mem.isa| 2 ++
On Wed, Jul 14, 2010 at 6:46 AM, Jiayuan Meng jerryh...@gmail.com wrote:
Thank you all for the suggestions!
=== I have the following questions: ===
1. how would M5 support plugins with pseudo instructions in the ISA?
Following Gabe's thoughts:
* M5 can provide general, customizable pseudo
For the classic (non-Ruby) m5 memory system, the coherence protocol
is pretty tightly integrated with the cache model. I don't know that
you can just disable it.
You certainly can set different block sizes on different caches (as I
think you already tried)... if you really want to pursue this
Can anyone remember why locked loads are tracked at a cache block
granularity (in the CacheBlk) class in the cache? It seems like it they
could be tracked by the cache object itself like it's done for physical
memory.
Thanks,
Ali
___
m5-dev
You're right that it could be done either way. I think the rationale
is that this way you don't need to search a list to see if your
address is on it. If the common case is that there are no locked
blocks in the entire cache though then that's not a big deal since the
list will be empty anyway.
You're right that it could be done either way. I think the rationale
is that this way you don't need to search a list to see if your
address is on it. If the common case is that there are no locked
blocks in the entire cache though then that's not a big deal since the
list will be empty
ARM has an instruction that clears the lock flag (CLREX). To implement
that in physical memory, it's easy enough, on the other hand with the cache
it requires calling clearLoadLocks() on every block in the cache.
Ali
On Thu, 15 Jul 2010 16:01:09 -0700, nathan binkert n...@binkert.org
wrote:
Alpha has to do the same thing on interrupts... the way this is
handled is that there's a per-thread lock flag in the CPU that gets
cleared on interrupts, and if that flag is not set then we fail the SC
without even sending it to the cache. (At least that's my
recollection of how it works.)
I think something like that could work, although I won't be advocating for
the forwarding snoop thing, since it seems as though ARM can support LLSC
on uncachable accesses.
Ali
On Thu, 15 Jul 2010 16:27:56 -0700, Steve Reinhardt
begin_of_the_skype_highlighting end_of_the_skype_highlighting
The uart is still a bit flaky and there is tons more todo, however:
m5 slave terminal: Terminal 0
[0.00] Linux version 2.6.28-arm2-eb-a9-arm-nano-tiny-up-wa-4.3.3
(alisa...@aus-bc5-b7) (gcc version 4.3.3 (Sourcery G++ Lite 2009q1-203) )
#2 Tue Jun 15 16:05:55 CDT 2010
[
Awesome :-).
Gabe
Quoting Ali Saidi sa...@umich.edu:
The uart is still a bit flaky and there is tons more todo, however:
m5 slave terminal: Terminal 0
[0.00] Linux version 2.6.28-arm2-eb-a9-arm-nano-tiny-up-wa-4.3.3
(alisa...@aus-bc5-b7) (gcc version 4.3.3 (Sourcery G++
Really? Doesn't that imply that you're snooping on uncacheables in real life?
On Thu, Jul 15, 2010 at 4:38 PM, Ali Saidi sa...@umich.edu wrote:
I think something like that could work, although I won't be advocating for
the forwarding snoop thing, since it seems as though ARM can support LLSC
You can mark a section of main memory as not cachable so it's not like an I/O
device. But, sort of, the description in the architecture reference manual
says there is a global monitor that checks the accesses.
Ali
On Jul 15, 2010, at 7:10 PM, Steve Reinhardt wrote:
Really? Doesn't that
Very cool!
On Thu, Jul 15, 2010 at 4:50 PM, Ali Saidi sa...@umich.edu wrote:
The uart is still a bit flaky and there is tons more todo, however:
m5 slave terminal: Terminal 0
[ 0.00] Linux version 2.6.28-arm2-eb-a9-arm-nano-tiny-up-wa-4.3.3
(alisa...@aus-bc5-b7) (gcc
Got it! I'll take a look at m5threads and prepare the patches to upload!
Thanks!
Jiayuan
On Thu, Jul 15, 2010 at 9:51 AM, Steve Reinhardt ste...@gmail.com wrote:
On Wed, Jul 14, 2010 at 6:46 AM, Jiayuan Meng jerryh...@gmail.com wrote:
Thank you all for the suggestions!
=== I have the
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