Create a Port atttribute in the associated Python object with the same
name that you match for in getPort(), then assign a pair of ports to
each other in your config file, and everything else should be
automatic. I hope that's enough to get you looking at the right
things in the existing code, any
Actually we looked into those files, especially AtomicSimpleCPU and
Memtester, but we are getting confused on how the cache ports are
getting connected properly. In our wrapper, we also had icacheport and
dcacheport, but not sure from where we can register them ( i.e. get the
Port::setPeer() ca
You need to use Port objects for this connection, just like the real
CPUs do (and the memtester). There isn't a lot of documentation on
the wiki, but I think the details are discussed in the tutorial.
Using the existing CPU or memtester code as an example is probably the
best route. Let us know i
Hi,
We are trying to connect a dummy cpu model to caches. So we require to
connect the icache and dcache ports of this dummy cpu model to that of M5
caches. Can anybody please tell us what is the best way to achieve this
connection ?
Arka & Rathijit
