changeset 199d31b47f7b in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=199d31b47f7b
description:
make BaseCPU the provider of _cpuId, and cpuId() instead of being
scattered
across the subclasses. generally make it so that member data is _cpuId
and
accessor functions are cpuId(). The ID val comes from the python
(default -1 if
none provided), and if it is -1, the index of cpuList will be given.
this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as
standard
switch.
diffstat:
12 files changed, 12 insertions(+), 19 deletions(-)
src/arch/sparc/ua2005.cc | 2 +-
src/cpu/base.cc | 5 +++--
src/cpu/base.hh | 5 +++++
src/cpu/o3/cpu.hh | 4 ----
src/cpu/o3/thread_context.hh | 2 --
src/cpu/ozone/cpu.hh | 2 --
src/cpu/simple/atomic.cc | 1 -
src/cpu/simple/timing.cc | 1 -
src/cpu/thread_context.cc | 1 -
src/cpu/thread_context.hh | 1 -
src/cpu/thread_state.cc | 4 ++--
src/sim/system.cc | 3 +--
diffs (truncated from 719 to 300 lines):
diff -r 93eb7f618517 -r 199d31b47f7b src/arch/alpha/locked_mem.hh
--- a/src/arch/alpha/locked_mem.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/arch/alpha/locked_mem.hh Sun Nov 02 21:56:57 2008 -0500
@@ -87,7 +87,7 @@
if (stCondFailures % 100000 == 0) {
warn("cpu %d: %d consecutive "
"store conditional failures\n",
- xc->readCpuId(), stCondFailures);
+ xc->cpuId(), stCondFailures);
}
// store conditional failed already, so don't issue it to mem
diff -r 93eb7f618517 -r 199d31b47f7b src/arch/mips/locked_mem.hh
--- a/src/arch/mips/locked_mem.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/arch/mips/locked_mem.hh Sun Nov 02 21:56:57 2008 -0500
@@ -85,7 +85,7 @@
if (stCondFailures % 10 == 0) {
warn("%i: cpu %d: %d consecutive "
"store conditional failures\n",
- curTick, xc->readCpuId(), stCondFailures);
+ curTick, xc->cpuId(), stCondFailures);
}
if (stCondFailures == 5000) {
diff -r 93eb7f618517 -r 199d31b47f7b src/arch/sparc/ua2005.cc
--- a/src/arch/sparc/ua2005.cc Tue Oct 28 21:13:21 2008 -0400
+++ b/src/arch/sparc/ua2005.cc Sun Nov 02 21:56:57 2008 -0500
@@ -257,11 +257,11 @@
temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
// Check that the CPU array is fully populated
// (by calling getNumCPus())
- assert(sys->getNumCPUs() > tc->readCpuId());
+ assert(sys->getNumCPUs() > tc->cpuId());
- temp |= tc->readCpuId() << STS::shft_id;
+ temp |= tc->cpuId() << STS::shft_id;
- for (x = tc->readCpuId() & ~3; x < sys->threadContexts.size(); x++) {
+ for (x = tc->cpuId() & ~3; x < sys->threadContexts.size(); x++) {
switch (sys->threadContexts[x]->status()) {
case ThreadContext::Active:
temp |= STS::st_run << (STS::shft_fsm0 -
diff -r 93eb7f618517 -r 199d31b47f7b src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Tue Oct 28 21:13:21 2008 -0400
+++ b/src/arch/x86/tlb.cc Sun Nov 02 21:56:57 2008 -0500
@@ -654,7 +654,7 @@
*/
// Force the access to be uncacheable.
req->setFlags(req->getFlags() | UNCACHEABLE);
- req->setPaddr(x86LocalAPICAddress(tc->readCpuId(), paddr - baseAddr));
+ req->setPaddr(x86LocalAPICAddress(tc->cpuId(), paddr - baseAddr));
}
#endif
return NoFault;
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/BaseCPU.py Sun Nov 02 21:56:57 2008 -0500
@@ -63,7 +63,7 @@
abstract = True
system = Param.System(Parent.any, "system object")
- cpu_id = Param.Int("CPU identifier")
+ cpu_id = Param.Int(-1, "CPU identifier")
numThreads = Param.Unsigned(1, "number of HW thread contexts")
function_trace = Param.Bool(False, "Enable function trace")
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/base.cc
--- a/src/cpu/base.cc Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/base.cc Sun Nov 02 21:56:57 2008 -0500
@@ -94,20 +94,28 @@
#if FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
- : MemObject(p), clock(p->clock), instCnt(0), interrupts(p->interrupts),
+ : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
+ interrupts(p->interrupts),
number_of_threads(p->numThreads), system(p->system),
phase(p->phase)
#else
BaseCPU::BaseCPU(Params *p)
- : MemObject(p), clock(p->clock),
+ : MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
number_of_threads(p->numThreads), system(p->system),
phase(p->phase)
#endif
{
// currentTick = curTick;
+ // if Python did not provide a valid ID, do it here
+ if (_cpuId == -1 ) {
+ _cpuId = cpuList.size();
+ }
+
// add self to global list of CPUs
cpuList.push_back(this);
+
+ DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
if (number_of_threads > maxThreadsPerCPU)
maxThreadsPerCPU = number_of_threads;
@@ -278,13 +286,9 @@
ThreadContext *tc = threadContexts[i];
#if FULL_SYSTEM
- int id = params()->cpu_id;
- if (id != -1)
- id += i;
-
- tc->setCpuId(system->registerThreadContext(tc, id));
+ system->registerThreadContext(tc);
#else
- tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc));
+ tc->getProcessPtr()->registerThreadContext(tc);
#endif
}
}
@@ -315,6 +319,8 @@
{
assert(threadContexts.size() == oldCPU->threadContexts.size());
+ _cpuId = oldCPU->cpuId();
+
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *newTC = threadContexts[i];
ThreadContext *oldTC = oldCPU->threadContexts[i];
@@ -323,12 +329,12 @@
CpuEvent::replaceThreadContext(oldTC, newTC);
- assert(newTC->readCpuId() == oldTC->readCpuId());
+ assert(newTC->cpuId() == oldTC->cpuId());
#if FULL_SYSTEM
- system->replaceThreadContext(newTC, newTC->readCpuId());
+ system->replaceThreadContext(newTC, newTC->cpuId());
#else
assert(newTC->getProcessPtr() == oldTC->getProcessPtr());
- newTC->getProcessPtr()->replaceThreadContext(newTC,
newTC->readCpuId());
+ newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->cpuId());
#endif
if (DTRACE(Context))
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/base.hh
--- a/src/cpu/base.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/base.hh Sun Nov 02 21:56:57 2008 -0500
@@ -80,8 +80,16 @@
Tick clock;
// @todo remove me after debugging with legion done
Tick instCnt;
+ // every cpu has an id, put it in the base cpu
+ // Set at initialization, only time a cpuId might change is during a
+ // takeover (which should be done from within the BaseCPU anyway,
+ // therefore no setCpuId() method is provided
+ int _cpuId;
public:
+ /** Reads this CPU's ID. */
+ int cpuId() { return _cpuId; }
+
// Tick currentTick;
inline Tick frequency() const { return Clock::Frequency / clock; }
inline Tick ticks(int numCycles) const { return clock * numCycles; }
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/base_dyn_inst.hh Sun Nov 02 21:56:57 2008 -0500
@@ -412,7 +412,7 @@
void dump(std::string &outstring);
/** Read this CPU's ID. */
- int readCpuId() { return cpu->readCpuId(); }
+ int cpuId() { return cpu->cpuId(); }
/** Returns the fault type. */
Fault getFault() { return fault; }
@@ -868,7 +868,7 @@
reqMade = true;
Request *req = new Request();
req->setVirt(asid, vaddr, size, flags, PC);
- req->setThreadContext(thread->readCpuId(), threadNumber);
+ req->setThreadContext(thread->cpuId(), threadNumber);
fault = cpu->translateDataReadReq(req, thread);
@@ -887,7 +887,7 @@
reqMade = true;
Request *req = new Request();
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->readCpuId(), threadNumber);
+ req->setThreadContext(thread->cpuId(), threadNumber);
fault = cpu->translateDataReadReq(req, thread);
@@ -942,7 +942,7 @@
reqMade = true;
Request *req = new Request();
req->setVirt(asid, vaddr, size, flags, PC);
- req->setThreadContext(thread->readCpuId(), threadNumber);
+ req->setThreadContext(thread->cpuId(), threadNumber);
fault = cpu->translateDataWriteReq(req, thread);
@@ -966,7 +966,7 @@
reqMade = true;
Request *req = new Request();
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->readCpuId(), threadNumber);
+ req->setThreadContext(thread->cpuId(), threadNumber);
fault = cpu->translateDataWriteReq(req, thread);
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/checker/cpu_impl.hh Sun Nov 02 21:56:57 2008 -0500
@@ -152,7 +152,7 @@
memReq = new Request(inst->threadNumber, fetch_PC,
sizeof(uint32_t),
IFETCH_FLAGS(thread->readPC()),
- fetch_PC, thread->readCpuId(),
inst->threadNumber);
+ fetch_PC, thread->cpuId(), inst->threadNumber);
bool succeeded = translateInstReq(memReq);
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/checker/thread_context.hh Sun Nov 02 21:56:57 2008 -0500
@@ -82,7 +82,7 @@
checkerTC->setCpuId(id);
}
- int readCpuId() { return actualTC->readCpuId(); }
+ int cpuId() { return actualTC->cpuId(); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/o3/cpu.cc Sun Nov 02 21:56:57 2008 -0500
@@ -62,7 +62,7 @@
using namespace TheISA;
BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
- : BaseCPU(params), cpuId(0)
+ : BaseCPU(params)
{
}
@@ -404,7 +404,6 @@
#endif
// Give the thread the TC.
this->thread[i]->tc = tc;
- this->thread[i]->setCpuId(params->cpu_id);
// Add the TC to the CPU's list of TC's.
this->threadContexts.push_back(tc);
@@ -611,7 +610,7 @@
}
#if FULL_SYSTEM
- TheISA::initCPU(src_tc, src_tc->readCpuId());
+ TheISA::initCPU(src_tc, src_tc->cpuId());
#endif
}
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/o3/cpu.hh Sun Nov 02 21:56:57 2008 -0500
@@ -74,15 +74,6 @@
BaseO3CPU(BaseCPUParams *params);
void regStats();
-
- /** Sets this CPU's ID. */
- void setCpuId(int id) { cpuId = id; }
-
- /** Reads this CPU's ID. */
- int readCpuId() { return cpuId; }
-
- protected:
- int cpuId;
};
/**
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/o3/fetch_impl.hh Sun Nov 02 21:56:57 2008 -0500
@@ -593,7 +593,7 @@
// Set the appropriate read size and flags as well.
// Build request here.
RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
- fetch_PC, cpu->readCpuId(), tid);
+ fetch_PC, cpu->cpuId(), tid);
memReq[tid] = mem_req;
diff -r 93eb7f618517 -r 199d31b47f7b src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh Tue Oct 28 21:13:21 2008 -0400
+++ b/src/cpu/o3/thread_context.hh Sun Nov 02 21:56:57 2008 -0500
@@ -75,11 +75,8 @@
/** Returns a pointer to this CPU. */
virtual BaseCPU *getCpuPtr() { return cpu; }
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
