changeset 11e6f4fa85c3 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=11e6f4fa85c3
description:
        new mp eio test

diffstat:

10 files changed, 1243 insertions(+), 1 deletion(-)
tests/SConscript                                                 |    1 
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini  |  263 +++++++
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt |  313 ++++++++
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr      |    6 
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout      |   12 
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini  |  257 +++++++
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt |  358 
++++++++++
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr      |    6 
tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout      |   12 
tests/quick/30.eio-mp/test.py                                    |   16 

diffs (truncated from 2540 to 300 lines):

diff -r c9056088f151 -r 11e6f4fa85c3 tests/SConscript
--- a/tests/SConscript  Wed Nov 05 16:19:17 2008 -0500
+++ b/tests/SConscript  Wed Nov 05 18:10:30 2008 -0500
@@ -223,7 +223,8 @@
                     't1000-simple-timing']
 
 else:
-    configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest']
+    configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
+                'simple-atomic-mp', 'simple-timing-mp']
 
 cwd = os.getcwd()
 os.chdir(str(Dir('.').srcdir))
diff -r c9056088f151 -r 11e6f4fa85c3 
tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini   Wed Nov 
05 18:10:30 2008 -0500
@@ -0,0 +1,526 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu0]
+type=AtomicSimpleCPU
+children=dcache dtb icache itb tracer workload
+clock=500
+cpu_id=0
+defer_registration=false
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu0.tracer
+width=1
+workload=system.cpu0.workload
+dcache_port=system.cpu0.dcache.cpu_side
+icache_port=system.cpu0.icache.cpu_side
+
+[system.cpu0.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.dcache_port
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu0.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu0.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.icache_port
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.itb]
+type=AlphaITB
+size=48
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu0.workload]
+type=EioProcess
+chkpt=
+errout=cerr
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+input=None
+max_stack_size=67108864
+output=cout
+system=system
+
+[system.cpu1]
+type=AtomicSimpleCPU
+children=dcache dtb icache itb tracer workload
+clock=500
+cpu_id=1
+defer_registration=false
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu1.tracer
+width=1
+workload=system.cpu1.workload
+dcache_port=system.cpu1.dcache.cpu_side
+icache_port=system.cpu1.icache.cpu_side
+
+[system.cpu1.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.dcache_port
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu1.dtb]
+type=AlphaDTB
+size=64
+
+[system.cpu1.icache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=1
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.icache_port
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu1.itb]
+type=AlphaITB
+size=48
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu1.workload]
+type=EioProcess
+chkpt=
+errout=cerr
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+input=None
+max_stack_size=67108864
+output=cout
+system=system
+
+[system.cpu2]
+type=AtomicSimpleCPU
+children=dcache dtb icache itb tracer workload
+clock=500
+cpu_id=2
+defer_registration=false
+dtb=system.cpu2.dtb
+function_trace=false
+function_trace_start=0
+itb=system.cpu2.itb
+max_insts_all_threads=0
+max_insts_any_thread=500000
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+phase=0
+progress_interval=0
+simulate_data_stalls=false
+simulate_inst_stalls=false
+system=system
+tracer=system.cpu2.tracer
+width=1
+workload=system.cpu2.workload
+dcache_port=system.cpu2.dcache.cpu_side
+icache_port=system.cpu2.icache.cpu_side
+
+[system.cpu2.dcache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+cpu_side_filter_ranges=
+hash_delay=1
+latency=1000
+max_miss_count=0
+mem_side_filter_ranges=
+mshrs=4
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev

Reply via email to