changeset b02bca5aed04 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=b02bca5aed04 description: stats: update 20.parser o3 now that it works. realview-o3 works too.
diffstat: tests/long/10.linux-boot/ref/arm/linux/realview-o3/status | 2 +- tests/long/20.parser/ref/x86/linux/o3-timing/simerr | 3 +- tests/long/20.parser/ref/x86/linux/o3-timing/simout | 9 +- tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt | 475 ++++++++++++++ 4 files changed, 483 insertions(+), 6 deletions(-) diffs (truncated from 518 to 300 lines): diff -r ea37585785ab -r b02bca5aed04 tests/long/10.linux-boot/ref/arm/linux/realview-o3/status --- a/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status Mon Apr 25 12:23:37 2011 -0500 +++ b/tests/long/10.linux-boot/ref/arm/linux/realview-o3/status Mon Apr 25 14:18:08 2011 -0700 @@ -1,1 +1,1 @@ -build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 FAILED! +build/ARM_FS/tests/fast/long/10.linux-boot/arm/linux/realview-o3 passed. diff -r ea37585785ab -r b02bca5aed04 tests/long/20.parser/ref/x86/linux/o3-timing/simerr --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simerr Mon Apr 25 12:23:37 2011 -0500 +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simerr Mon Apr 25 14:18:08 2011 -0700 @@ -4,5 +4,4 @@ For more information see: http://www.m5sim.org/warn/437d5238 warn: instruction 'fldcw_Mw' unimplemented For more information see: http://www.m5sim.org/warn/437d5238 -m5.fast: build/X86_SE/arch/x86/emulenv.cc:49: void X86ISA::EmulEnv::doModRM(const X86ISA::ExtMachInst&): Assertion `machInst.modRM.mod != 3' failed. -Program aborted at cycle 582313255000 +hack: be nice to actually delete the event here diff -r ea37585785ab -r b02bca5aed04 tests/long/20.parser/ref/x86/linux/o3-timing/simout --- a/tests/long/20.parser/ref/x86/linux/o3-timing/simout Mon Apr 25 12:23:37 2011 -0500 +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/simout Mon Apr 25 14:18:08 2011 -0700 @@ -5,9 +5,9 @@ All Rights Reserved -M5 compiled Apr 21 2011 13:30:37 -M5 started Apr 21 2011 13:42:45 -M5 executing on maize +M5 compiled Apr 23 2011 16:56:34 +M5 started Apr 23 2011 17:38:09 +M5 executing on victors command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -71,3 +71,6 @@ we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended + the five best costumes got prizes +No errors! +Exiting @ tick 584102039000 because target called exit() diff -r ea37585785ab -r b02bca5aed04 tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt --- a/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt Mon Apr 25 12:23:37 2011 -0500 +++ b/tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt Mon Apr 25 14:18:08 2011 -0700 @@ -0,0 +1,475 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 88955 # Simulator instruction rate (inst/s) +host_mem_usage 246024 # Number of bytes of host memory used +host_seconds 17188.43 # Real time elapsed on the host +host_tick_rate 33982273 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 1528988756 # Number of instructions simulated +sim_seconds 0.584102 # Number of seconds simulated +sim_ticks 584102039000 # Number of ticks simulated +system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.BPredUnit.BTBHits 218742072 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 237579384 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 16731555 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 252612908 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 252612908 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.commit.branchMispredicts 16763223 # The number of times a branch was mispredicted +system.cpu.commit.branches 149758588 # Number of branches committed +system.cpu.commit.bw_lim_events 41097639 # number cycles where commit BW limit reached +system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 795955462 # The number of squashed insts skipped by commit +system.cpu.commit.committed_per_cycle::samples 1035309655 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.476842 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.993609 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 433213212 41.84% 41.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 271303976 26.21% 68.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 102660477 9.92% 77.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 102477093 9.90% 87.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 38291141 3.70% 91.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 25044351 2.42% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10787246 1.04% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 10434520 1.01% 96.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 41097639 3.97% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1035309655 # Number of insts commited each cycle +system.cpu.commit.count 1528988756 # Number of instructions committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.function_calls 0 # Number of function calls committed. +system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. +system.cpu.commit.loads 384102160 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.refs 533262345 # Number of memory references committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.committedInsts 1528988756 # Number of Instructions Simulated +system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated +system.cpu.cpi 0.764037 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.764037 # CPI: Total CPI of All Threads +system.cpu.dcache.ReadReq_accesses 323639192 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15916.826695 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8444.942006 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 320628262 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 47924451000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.009303 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 3010930 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1248670 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 14882183500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.005445 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 1762260 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 23726.182533 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18050.899847 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 147539972 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 38441849000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.010862 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1620229 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 607112 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 18287673500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.006792 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1013117 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 185.317160 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.demand_accesses 472799393 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 18648.960228 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency +system.cpu.dcache.demand_hits 468168234 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 86366300000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.009795 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4631159 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1855782 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33169857000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005870 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 2775377 # number of demand (read+write) MSHR misses +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.occ_blocks::0 4088.515779 # Average occupied blocks per context +system.cpu.dcache.occ_percent::0 0.998173 # Average percentage of cache occupancy +system.cpu.dcache.overall_accesses 472799393 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 18648.960228 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 11951.477943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 468168234 # number of overall hits +system.cpu.dcache.overall_miss_latency 86366300000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.009795 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4631159 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1855782 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33169857000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005870 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 2775377 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.dcache.replacements 2529347 # number of replacements +system.cpu.dcache.sampled_refs 2533443 # Sample count of references to valid blocks. +system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.tagsinuse 4088.515779 # Cycle average of tags in use +system.cpu.dcache.total_refs 469490463 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 2268948000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 2231104 # number of writebacks +system.cpu.decode.BlockedCycles 187291575 # Number of cycles decode is blocked +system.cpu.decode.DecodedInsts 2489806075 # Number of instructions handled by decode +system.cpu.decode.IdleCycles 422005844 # Number of cycles decode is idle +system.cpu.decode.RunCycles 404270583 # Number of cycles decode is running +system.cpu.decode.SquashCycles 108207267 # Number of cycles decode is squashing +system.cpu.decode.UnblockCycles 21741653 # Number of cycles decode is unblocking +system.cpu.fetch.Branches 252612908 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 188594062 # Number of cache lines fetched +system.cpu.fetch.Cycles 440470513 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 3788635 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 1360923559 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 78504 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 19199509 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.216240 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 188594062 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 218742072 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.164971 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1143516922 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.221243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.208291 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 707206433 61.84% 61.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32665502 2.86% 64.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 37223305 3.26% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33654778 2.94% 70.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21116720 1.85% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 40194771 3.52% 76.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 44517058 3.89% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36097891 3.16% 83.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 190840464 16.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 1143516922 # Number of instructions fetched each cycle (Total) +system.cpu.fp_regfile_reads 40 # number of floating regfile reads +system.cpu.icache.ReadReq_accesses 188594062 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 6510.591789 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 3406.338578 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 188336504 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1676855000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001366 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 257558 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1428 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 872465500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001358 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 256130 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 16890.533363 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.demand_accesses 188594062 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 6510.591789 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency +system.cpu.icache.demand_hits 188336504 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1676855000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001366 # miss rate for demand accesses +system.cpu.icache.demand_misses 257558 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1428 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 872465500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001358 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 256130 # number of demand (read+write) MSHR misses +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.occ_blocks::0 960.715295 # Average occupied blocks per context +system.cpu.icache.occ_percent::0 0.469099 # Average percentage of cache occupancy +system.cpu.icache.overall_accesses 188594062 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 6510.591789 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 3406.338578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 188336504 # number of overall hits +system.cpu.icache.overall_miss_latency 1676855000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001366 # miss rate for overall accesses +system.cpu.icache.overall_misses 257558 # number of overall misses +system.cpu.icache.overall_mshr_hits 1428 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 872465500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001358 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 256130 # number of overall MSHR misses +system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses +system.cpu.icache.replacements 9707 # number of replacements +system.cpu.icache.sampled_refs 11150 # Sample count of references to valid blocks. +system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.tagsinuse 960.715295 # Cycle average of tags in use +system.cpu.icache.total_refs 188329447 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.writebacks 6 # number of writebacks +system.cpu.idleCycles 24687157 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.branchMispredicts 18167511 # Number of branch mispredicts detected at execute +system.cpu.iew.exec_branches 173444431 # Number of branches executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_rate 1.602205 # Inst execution rate +system.cpu.iew.exec_refs 612750445 # number of memory reference insts executed +system.cpu.iew.exec_stores 165978925 # Number of stores executed +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.iewBlockCycles 9685611 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 586119276 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 9659 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 2269927 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 223085364 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2324941378 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 446771520 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 30325762 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1871702722 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 1004270 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewLSQFullEvents 42321 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 108207267 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 1500742 # Number of cycles IEW is unblocking +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.forwLoads 122021898 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.ignoredResponses 146459 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.memOrderViolation 2443893 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.rescheduledLoads 1254 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.squashedLoads 202017116 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedStores 73925179 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 2443893 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 2771097 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 15396414 # Number of branches that were predicted taken incorrectly +system.cpu.iew.wb_consumers 2110704618 # num instructions consuming a value +system.cpu.iew.wb_count 1858331416 # cumulative count of insts written-back +system.cpu.iew.wb_fanout 0.678632 # average fanout of values written-back +system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu.iew.wb_producers 1432391344 # num instructions producing a value +system.cpu.iew.wb_rate 1.590759 # insts written-back per cycle +system.cpu.iew.wb_sent 1864643959 # cumulative count of insts sent to commit +system.cpu.int_regfile_reads 3111234049 # number of integer regfile reads +system.cpu.int_regfile_writes 1733847214 # number of integer regfile writes _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
