Hi,
I have a topology as follows:
ARM_CPU <-> L1_Data_Cache <-> L2_Coherent_Bus <-> L2_Cache <->
Memory_Coherent_Bus <-> My_Bridge
My_Bridge has a SimpleMemory to connect with Memory_Coherent_Bus.
If My_Bridge has to snoop into ARM_CPU, are these assumptions correct for a
Snoop Read transacti
I'm a newbie and I apologize if this has been answered before, but I
couldn't find anything that solved my problem in the documentation or the
mailing list.
I'm trying to get Ruby to work in the most basic vanilla case possible and
not having any luck.
I had recently updated with mercurial to the
Thank you so much!
Yanqi
From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of
Steve Reinhardt [ste...@gmail.com]
Sent: Wednesday, June 12, 2013 9:05 PM
To: gem5 users mailing list
Subject: Re: [gem5-users] Thread switch
I think suspendConte
Hi Yongbing,
You need to figure out what the serial number of the instruction that causes
this issue is and the get an debug trace with --debug-flags=O3CPUAll with that
serial number and see what happens in the execution to it.
Thanks,
Ali
On Jun 4, 2013, at 9:01 PM, huangyongbing wrote:
> H
The operations you mention are floating point loads and stores.
Ali
On Jun 9, 2013, at 10:50 AM, Yuanbo Fan wrote:
> Hi everyone,
>
> I tried to run some floating point benchmarks on gem5 in atomic cpu mode, but
> the instruction traces I got from the ARM FS simulation are mostly integer
> i
Hi Diviya,
Are you sure the shared object is available in that directory? Have you set
LIBRARY_PATH?
Thanks,
Ali
On Jun 10, 2013, at 6:16 AM, Jain Diviya-B12553 wrote:
> Hi,
>
> I am trying to build gem5 shared library using following command:
> scons build/ARM/libgem5_debug.so
>
> I h
I think suspendContext() and activateContext() might be the calls you are
looking for.
Steve
On Wed, Jun 12, 2013 at 3:24 PM, Yanqi Zhou wrote:
> Great to know!
> Thanks again.
> One more question: what is the best way to stall a cpu? There are ways
> such as inserting cache stalls. Can you s
Great to know!
Thanks again.
One more question: what is the best way to stall a cpu? There are ways such as
inserting cache stalls. Can you suggest a easy way to stall one cpu without
affecting another cpu?
Thanks,
Yanqi
From: gem5-users-boun...@gem5.org [gem5-use
Normally the CPUs operate independently, so if one stalls, the others just
keep on going.
CPU switching etc. is covered here:
http://gem5.org/Checkpoints#Switchover.2FFastforwarding
Steve
On Wed, Jun 12, 2013 at 2:18 PM, Yanqi Zhou wrote:
> Thanks Steve,
> I have a question regarding cpu swi
Hi,
I am fairly new to GEM5. I was trying to run multiple binaries of 'hello
world' program on a single CPU in SE mode. But I am getting an error message
the command which I am using : build/X86/gem5.opt configs/example/se.py
--cpu-type=detailed --caches --smt -c tests/test-progs/hello/bin/
x86/l
Thanks Steve,
I have a question regarding cpu switch. What triggers the cpu switch in gem5 by
default? What happens to cpu1 if cpu0 is stalled for a long time (due to a
cache miss or something)?
Yanqi
From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org
switchOut() is used for fast forwarding or sampling, where you are using
two different CPU models (one simpler and one more detailed) to represent
the same logical CPU.
Steve
On Wed, Jun 12, 2013 at 12:59 PM, Yanqi Zhou wrote:
> Hi Steve,
> I also tried : cpu->switchOut();
> This results in e
Hi,
I'm struggling to get interrupts to work properly on x86.
I've added an instance of X86IntelMPIOIntAssignment to the MP table in
makeX86system(), but the kernel driver still says it can't find an
mptable entry for this device's interrupt:
igb :00:02.0: can't find IRQ for PCI INT A;
Hi Maceij,
I plan to do a fair bit of work with gem5 and PCI (on x86), but I'm not
yet fully up to speed on its architecture.
The short answer is no, it doesn't implement the full protocol.
So far I can tell you:
* PCI Config evidently "works", but it is nothing like how real
hardware does
If you have one thread per CPU, then there's really no "switching" to be
done. I'm not clear on what you're trying to do, but would simply stalling
and restarting the CPUs at different times achieve your goals? All that
requires is controlling when the tick events on the CPU objects get
scheduled
Hi Steve,
I also tried : cpu->switchOut();
This results in error:
build/ALPHA/sim/eventq.hh:491: void EventQueue::schedule(Event*, Tick):
Assertion `(UTick)when >= (UTick)curTick()' failed.
Program aborted at cycle -41326055636
Is that because the tick of next event does not match current tick? I
Hi Steve,
I am running full system mode. Threads are on different CPUs. For instance I
allocate 4 CPUs for 4-thread programs.
Thanks,
Yanqi
From: gem5-users-boun...@gem5.org [gem5-users-boun...@gem5.org] on behalf of
Steve Reinhardt [ste...@gmail.com]
Sent: Wednes
Hi Yanqi,
It's hard to answer your question without more information about your
situation. For example, are you running in full system mode or syscall
emulation mode? Are you talking about threads on the same CPU, or on
different CPUs?
Steve
On Tue, Jun 11, 2013 at 5:22 PM, Yanqi Zhou wrote
Hi Mahshid,
It uses gem5's stats package, which are opaque variables (only computed
should never be read) and printed out when dump_stats is called -- either
by the psuedo instruction or at the end of the simulation.
There is a gem5_reset_stats() psuedo instruction that resets all the gem5
stats,
Hi,
I am fairly new to GEM5. I was trying to run multiple binaries of 'hello
world' program on a single CPU in SE mode. But I am getting an error message
the command which I am using : build/X86/gem5.opt configs/example/se.py
--cpu-type=detailed --caches --smt -c
tests/test-progs/hello/bin/x86/li
Hi everyone,
I want to make you aware of a full-time Server Performance Modeling
Engineer position that is open at AMD in Sunnyvale, CA. Familiarity with
gem5 is a plus for this position, so I thought it would be relevant to the
list. See the official posting for more details:
https://amd.apply2
Hi Malek,
Thanks a lot for the update. I will get the recent revision. Does this
revision calculate cache miss rates periodically when dumping stats
periodically?
And about my calculation, I actually sum up L1 misses across all L1 caches
and consider this to be overall L2 accesses. In fact I am c
The patch was incorporated into some other recent ruby stat changes
recently (1-2 weeks): specifically the removal of the cache profiler, and
the counting of hits/misses directly in the sm file. So you should probably
update.
The other thing is, I think your complicating your calculations a bit:
Thanks for your reply Maxime. But is there anything wrong with the way I
calculate the rates? I see that the patch has been submitted for review
long time back, but has not been applied to the gem5 release yet. Is this
patch reliable?
Thanks.
Mahshid
On Wed, Jun 12, 2013 at 7:29 AM, Maxime Chéra
Have a look to http://reviews.gem5.org/r/1467/ but the support of MESI_CMP
is not correct, you'll have to do some changes.
2013/6/12 Mahshid Sedghi
> Hi all,
>
> I'm trying to calculate L1 and L2 cache miss rates for a full system
> simulation using ruby (MESI_CMP_directory) + garnet. I dump st
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