I want to create checkpoints using MOESI_hammer +ruby.
I used command:
./build/X86_MOESI_hammer/gem5.fast
configs/example/se.py -n 1 --cpu-type=timing --bench bzip2 --ruby -I
10 --checkpoint-dir=tmpdir --checkpoint-at-end
However I only got two files in the checkpoint folder:
m5.cpt
syst
Prateek,
Don't know what is config.dot.py but with config.dot.pdf you can
easily verify the connections.
On 4/4/14, Prateek Gupta wrote:
> Hello Andreas,
>
>
> Thanks for your reply.
> Do I need to extend fs.py or se.py? I have tried making changes in
> CacheConfig.py, Caches.py and
> Options.py
Sanem,
maybe you put sleep() somewhere in the code that never executes! Can
you confirm that by breakpoints?
On 4/4/14, Sanem Arslan wrote:
> Hi all,
>
> I am using classic memory system and I have added several codes to
> the "cache_impl.hh" and "blk.hh" files. However I cannot see the
> perfor
I am currently trying to use the gem5 prefetcher and
have edited the CacheConfig.py
file to include the default StridePrefetcher()
attached to both the data and the l2 cache. However, I am always
receiving 0's for all prefetcher data
in the stats.txt file and can't seem to figure out why.
I
Hi all,
I am using classic memory system and I have added several codes to
the "cache_impl.hh" and "blk.hh" files. However I cannot see the
performance overhead of these added codes on the gem5 execution time.
I have increased cache latency parameters from "CacheConfig.py" file
and I can
Hi,
I’m trying to figure out how to modify cache size of gem5 with ruby memory
subsystem, but seems if the l1d cache size is lower than 64kB, there will be a
kernel panic under SE model.
The command I’m using is:
./build/X86/gem5.opt configs/example/se.py --ruby --caches —l1d_size=64kB -c
./t
Hello Andreas,
Thanks for your reply.
Do I need to extend fs.py or se.py? I have tried making changes in
CacheConfig.py, Caches.py and
Options.py as follows:
Options.py: I add this new option
parser.add_option("--l3cache", action="store_true")
Caches.py: I add the L3 cache
class L1Cache(B
Hi Prateek,
The classic memory model has all the bits you need. There is a DRAM
controller, and you can create as many levels of caches as you want (and
stripe across as many different L3s as you please). You should be fine
simply extending the fs.py or se.py script to make sure one or more L3s
ar