Hi all,
Just to clarify, if you want to see what clock speed the CPU was run at,
the best place to look is in the m5out directory where you have a
config.ini/json/dot that contains a snapshot of all the parameters that
were used. In this particular case, sim_ticks in not in cycles, so you
would ha
There's no fundamental reason it shouldn't work, though it likely hasn't
been tested. It's just a matter of adding a NIC to the PCI bus in an x86
system (if there isn't already one there), using the existing dual-node
framework to instantiate two of those systems, and hooking up the two NICs
with
Hi All -
I want to simulate a server app with the load generator running on the
side, x86 and multi-core.
Is the "dual full system" option even viable for x86? The scripts (i.e.
fs.py, FSConfig.py, et al.) appear to support only Alpha and ARM.
Thank you,
Pete Stevenson
_
I have a related post on the mailing list about this, and I indicate a
workaround to the problem. It's not ideal, but it works. Keep in mind, that
just because you didn't modify the protocol, doesn't mean errors aren't
bound to occur.
Malek
On Sun, Apr 27, 2014 at 3:02 AM, sunlong wrote:
> Hi
Hi all,
I am trying to modify MOESI_hammer protocol. First I add l3 cache. Second,
I add flush all cachelines by issuing FlushReq through Sequencer.
I meet some problems when run some bench mark:
1. Tried to read unmapped address 0x40.
2. fatal: Ruby functional read failed for address.
I have s
