Hi Ciro,
Thank you for the quick response. I think I wasn't clear on my question.
What I was asking is basically the parameters required for modelling an ARM
cortex a76 in gem5. I think you answered the question.
I modified the ex5_big.py file in configs/common/cores/arm/ location with
few
Hi everyone,
I have started working with gem5 from past 2 weeks and am trying to
simulate a multi-core CPU system with RISC-V ISA on gem5.
I have written a C file where I use inline assembly snippet to grab the
value of mhartid (Hardware Thread id), marchid and mstatus.
I used this command to
On 3/1/19 12:31 AM, siva sankar wrote:
> Hi all,
>
> Can someone help me or direct me on how to configure the ARM cortex a76
> in gem5?
>
What do you mean more precisely? I can't find any references to A76 in-tree.
For the ISA interface purely, we have very few "enable this feature"
flags in the
