[gem5-users] Questions about modeling variable dram packet delay?

Hi, all, I am trying to model a variable latency dram system, in which every dram packet has different latency instead of a fixed latency. I tried to add the latency in the readyTime for each dram pkt. But it disturbed the power event because some refresh events were not satisfied in time and t

[gem5-users] Memory consistency using different ISAs with classic memory system

I have a question regarding the memory consistency model (MCM) when using different ISAs with the classic memory system. My understanding is that the design of gem5 mostly decouples the ISA semantics from the microarchitectural implementation in order to more easily support multiple ISAs. There is