Re: [gem5-users] Indeterministic gem5 behavior

Sorry for the spam. I just forgot to mention that the system configuration I am using is mainly from https://github.com/darchr/gem5/tree/jason/kvm-testing/configs/myconfigs. Shehab Y. Elsayed, MSc. PhD Student The Edwards

Re: [gem5-users] Indeterministic gem5 behavior

I have set up a repo with gem5 that demonstrates the problem. The repo includes the latest version of gem5 from gem5's github repo with a few patches applied to get KVM working together with the kernel binary and disk image I am using. You can get the repo at

Re: [gem5-users] x86 CMP Instruction Exec Logic

CMP is a class of macro-ops which is first decoded into microops here: src/arch/x86/isa/insts/general_purpose/compare_and_test/compare.py So to compare a register value with a memory value, we have the variant CMP_R_M that is decoded as: def macroop CMP_R_M { ld t1, seg, sib, disp sub t0,

[gem5-users] x86 CMP Instruction Exec Logic

Hello Members, Can somebody help me identify this. Where is x86 CMP instruction execute logic implemented ? I can see CMP encoding here. src/arch/x86/decoder/one_byte_opcode.isa But I am not sure where is the execute logic implemented. Thanks Shah

Re: [gem5-users] Classic memory model and responding to snoops

Hi Kevin, On 29/07/2019 03:35, Kevin Smith wrote: > Hi all, > > I have a question regarding the classic memory model, about how a cache > knows when to respond to a peer (neighbor) cache. Please bear with me as > I try to diagnose what happens and let me know where/if I'm wrong :) > In general,