Hi Abbas,
Have you solved this problem?
I think one of the reason might be that the latency of HBM is higher than DDR4
even if the bandwidth of HBM is higher than DDR4. Maybe you can use multiple
channel of HBM to solve this problem.
Regards,
Chenfeng Zhao
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Hi, All,
I am trying to read the code in src/cpu, I find that a lot namespace like
TheISA are used in cpu code, but sometimes I can not find them. And also, I
find some of them are defined in build/X86 directory after we build them. Does
anyone knows some hints about where these namespace are d