Hi all,
Since m5ops are not available for RISCV, I am trying to define a region of
interest by using misc registers. I added a custom register to
https://github.com/gem5/gem5/blob/master/src/arch/riscv/registers.hh
How can I read the register that I added or write to it so that I can start
collec
Hi all,
I am aware that we can set latencies on an opClass basis (ex. MemRead) for the
O3_ARM_v7a CPU, but is it possible to set instruction-specific (ex. LDREX)
latencies?
Thanks,
Paul
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Hi All,
I have run the following command but the rcS script is not working. Any help
would be appreciated.
The output on system.terminal
ALSA device list:
No soundcards found.
input: AT Raw Set 2 keyboard as
/devices/smb.14/motherboard.15/iofpga.17/1c06.kmi/serio0/input/input0
input: to
Hi all,
Is paging possible in system emulation mode? I want to simulate a system
with RISCV isa and provide an input bigger than RAM size.
Best,
Muhammet
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