Hi,
You need to decode the trace file using gem5/util/decode_packet_trace.py.
This python file dumps the traces to ASCII.
More information on the fields can be found here:
https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU
Serhat
From: gem5-users
Oh Thanks Serhat.
python2 and pypl in protobuf decoded my packet.
2020년 3월 17일 (화) 오후 10:21, Serhat Gesoglu 님이
작성:
> Hi,
> You need to decode the trace file using gem5/util/decode_packet_trace.py.
> This python file dumps the traces to ASCII.
> More information on the fields can be found here:
>
Hi,
I am sure there are much better ways to do this but so far there are not any
other suggestions.
One solution could be creating an event and scheduling it to monitor the number
of misses.
When the number reaches N, exitSimLoop exits the simulation with a cause, such
as "Encountered N misses"
With the help of many people on gem5-users, the traffic between the CPU and
the L1DCache could be observed using Commmonitor.
But i'm trying to find real data transmitting bits between L1D cache and
CPU.
Sadly, the size of the data transmitted by Commonitor could be determined,
but not observed