Hi All,
I run the following command to take checkpoint and it works well. But when i
use --cpu-type=DerivO3CPU instead of AtomicSimpleCPU the system crash. I want
DerivO3CPU as cpu type. Any help would be appreciated.
build/ARM/gem5.opt configs/example/fs.py --os-type=android-ics
--machine
Thank you, Ciro. Turned out that by disabling most of the (classic) cache
stat handlers, I was able to free up a lot of memory.
Subhankar Pal | PhD Candidate, CSE | University of Michigan
On March 25, 2020 at 4:38:52 AM, Ciro Santilli (ciro.santi...@gmail.com)
wrote:
I would try to put print
Hi all,
>From my understanding,* master simObjects (CPUs, GPUs) generate requests *to
the slave simObjects(L1private split cache, membus, L2 cache etc.), slaves
responses to the requests.
I want to see both *requests* and *response* packets. I have attached a
communication monitor in addPrivateSpl
if Commmonitor exist between L1D cache and CPU, output is Packet
information encoding protobuf.
Output file Packet Information is this link
https://www.gem5.org/documentation/general_docs/cpu_models/TraceCPU .
By changing commmonitor, I would also like to see information about the
data contained
I would try to put prints/PDB on src/python/m5/stats/__init__.py where
enable is called.
On Wed, Mar 25, 2020 at 5:35 AM Subhankar Pal wrote:
>
> Hi,
>
> I am trying to run simulations in SE mode with a 1000+ (simple) cores. I get
> the following error once m5.instantiate() is called.
> Tracebac
You have to either fully boot Android on fs.py or find some userland
setup which I don't know about for SE.
I don't have a fully automated Android boot setup, so just try it out
and tell if it fails and how.
For plain Java, it is much more likely that you will be able to run in
SE: but will need
