That version of gem5 is a few years old and doesn't have the updates to the
m5 utility that made it use scons. In that version, you need to use make.
Gabe
On Fri, Nov 13, 2020 at 7:43 PM krishnan gosakan via gem5-users <
gem5-users@gem5.org> wrote:
> Hi all,
> I am trying to compile m5 utils. I
Hi all,
I am trying to compile m5 utils. I followed the documentation available at
https://www.gem5.org/documentation/general_docs/m5ops/
I am using
https://gem5.googlesource.com/public/gem5/+/f0364a2b08f8919347164e9aad82ca3a0167eb4b
In the above repo, utils/m5 directory has no scons file and I am
Hey,
I think the method that may help you here is `disassemble` in
static_inst.hh:
https://gem5.googlesource.com/public/gem5/+/refs/tags/v20.1.0.1/src/cpu/static_inst.hh#340.
I imagine, what you want to do is something like `print
(*address).disassemble()`.
It may also be worth looking into the g
Hey,
These warnings are fine (I get them), they won't affect what you're trying
to do. The compilation was successful.
I see Hoa is already handling your "When gem5 is debugged, how to judge
the current position of data?" question (
https://www.mail-archive.com/gem5-users@gem5.org/msg18709.html)
Hey Mahyar,
I think I didn’t describe my problem correctly. I want to send one packet per
cycle over the XBar (for 4B/cycle, for example), however, I am only managing to
send one packet every two cycles (2B/cycle). It seems like the
pkt->payloadDelay is getting set to include the time to transf
You have to use:
ThreadID tid = [...]
ThreadContext * tc = cpu->getContext(tid)
ContextID = tc->contextId();
Kind Regards
Giacomo
From: Farhad Yusufali
Sent: 13 November 2020 16:11
To: Adrian Herrera ; gem5 users mailing list
Cc: Giacomo Travaglini
Subject: Re: [gem5-users] Re: ThreadID vs
Got it, thanks. If I have a ThreadID and know what CPU it's running on, how
would I go about retrieving the corresponding ContextID?
Thanks,
Farhad
From: Adrian Herrera
Sent: November 13, 2020 10:53 AM
To: gem5 users mailing list
Cc: Farhad Yusufali ; Giacomo Tr
Hi Farhad,
To clarify:
* CPU ports, in all simple, minor and O3 configurations, tag generated
Requests with ContextID.
* Outgoing Packets from CPU ports have a Request pointer inside, via which
you can get the ContextID.
Kind regards,
Adrian.
From: Giacomo Travaglini via gem5-users
R
Hi Tracy,
I think you can put scheduleInstStop() and m5.simulate() in a loop to do that.
Regards,
Hoa Nguyen
On 11/10/20, Tracy Mac via gem5-users wrote:
> Hi All!
> I am trying to limit instructions number repeatedly,stop the simulation
> when the instruction is limited, do other operations, a
HI Farhad,
ThreadID -> index of the thread within the CPU
ContextID -> global index of the thread within the System
As you can imagine they differ in a MP simulation, with multiple CPUs per System
Kind Regards
Giacomo
From: Farhad Yusufali via gem5-users
Sent: 13 November 2020 14:25
To: gem5
Hello,
Just following up on this, any help would be appreciated.
Thanks,
Farhad
From: Farhad Yusufali via gem5-users
Sent: November 11, 2020 7:31 PM
To: gem5-users
Cc: Farhad Yusufali
Subject: [gem5-users] ThreadID vs ContextID vs threadNumber
EXTERNAL EMAIL:
Hey,
I've tried my hand at this problem before and it can be a bit tricky but
with patience and some python scripts you can get what you want.
First, depending on what memory address you are interested in, you will
probably need to extract the physical address. Or if you can just pick an
address
Hi,
I assume that you want to keep track of a piece of data at a specific
virtual/physical address. I don't know a definite answer to this, but
one thing you can do is to use the gem5 logging system (i.e. DPRINTF
and the like) and figure out what flags you should enable to keep
track of transactio
Hi Duc Anh,
Can you please confirm that this change,
https://gem5-review.googlesource.com/c/public/gem5/+/36296, fixes the
stats error?
Regards,
Hoa Nguyen
On 11/12/20, Hoa Nguyen wrote:
> Hi Duc Anh,
>
> I think the stats error is related to this change,
> https://gem5-review.googlesource.com/
Hi Duc Anh,
To answer the question about simulation speed, I believe the
difference between SE mode and FS mode is minimal. In addition to
that, kernel interactions, like process scheduler and page table
walks, have significant impact on system performance, so in most
cases, I believe it is more a
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