[gem5-users] How to modify the gem5 simulator code?

Hi. I built a system that has two cpu that have private L1 caches, shared L2 caches, memory controller that has nvm and dram. Workload has been assigned to each cpu. I want to use only the dram for cpu0 and nvm for cpu1. Therefore, I thought it was necessary to modify some of the code on

[gem5-users] Need Help For Applying a Patch

Hello everyone! I am trying to implement a patch, but for some reason I am unable to do it. I feel like I might be missing a step in between somewhere. I am using the instructions given in this site to import the patch: https://synergy.ece.gatech.edu/tools/garnet/mercurial-patches-for-gem5garnet/ I

[gem5-users] m5ops for riscv

Dear all, I would like to use the m5ops functions such as "m5_reset_stats" in my own c++ program. I have done it for x86, however, I would like to do it for RISC-V. For X86 I performed the following: scons -C util/m5 build/x86/out/m5 gcc -static -I include -o main.out main.c util/m5/build/x86/out

[gem5-users] Re: X86 Elastic Trace Replay

Hey Patrick, This isn't exactly an answer to your question, but you can find a similarly "simple" x86 FS configuration in the gem5-resources repository. E.g., https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable/src/boot-exit/configs/system/ . I'm sure that it's *possible* to d

[gem5-users] Re: gem5 stats , LLC average miss latency

Hi Arun, That time is in simulator *ticks*, not cycles. By default, the tick time is 1ps, so that would be an average latency of 3.8us, which is high, but seems possible for non-volatile memory. Cheers, Jason On Sun, Nov 15, 2020 at 11:43 PM Arun Kavumkal via gem5-users < gem5-users@gem5.org> wr

[gem5-users] Re: A question regarding to VIPT/PIPT

Hi Ayaz, (1) I want to model VIPT cache in gem5 under Ruby system, but Ruby does not seem to call the method in the classic system, that is, the script in the src/mem/cache . Which files should I modify to model VIPT in Ruby? (2) According to my understanding of VIPT and PIPT, the latency diffe

[gem5-users] Tag lookup latency and Data access latency in Ruby

Hello everyone: I have two questions about the cache access parameters of Ruby: (1) In classic system, tag_latency = Param.Cycles("Tag lookup latency") and data_latency = Param.Cycles("Data access latency") In Ruby system, what is the corresponding tag_latency and data_latency ? I only find dataA

[gem5-users] Re: Error When Recovering Checkpoints in SE Mode

To further clarify, I did run util/cpt_upgrader.py on the checkpoint to no avail. *Chongzhi Zhao* On Tue, Nov 17, 2020 at 1:51 PM Chongzhi Zhao wrote: > Hi, > > I attempted to recover some Simpoint checkpoints for x86 in SE mode and > got the error below. I did see the warning on using util/cp