[gem5-users] Re: Flushing the Caches

Hi Sherif and Arth, I had a similar problem. I resolved it by coming up with a somewhat hacky solution that utilizes the “forEachBlk” function call in the base tags. For context, I needed the main memory state to be consistent between a task running some component on both big and little CPU

[gem5-users] Re: Flushing the Caches

Hi Sherif, Maybe the functionality is already there, but it may not be as easy as it sounds depending on what you mean by "flushing". Functionally invalidating cache lines is staightforward, but anything that is dirty in the cache should be written back, and this may be harder to handle

[gem5-users] Re: ISSUES FACING WHILE INTEGRATING GEM5 AND DRAMSIM3

Ok thank you Best regards, Monica Bhargavi Kodali. Get Outlook for Android From: Mahyar Samani via gem5-users Sent: Monday, March 29, 2021 12:23:00 PM To: gem5 users mailing list Cc: hauru...@gmail.com ; Mahyar Samani Subject:

[gem5-users] Re: ISSUES FACING WHILE INTEGRATING GEM5 AND DRAMSIM3

Hello, I would say overall DRAMSim3 is more accurate and to be honest it is much easier to use than DRAMSim2. I am also doing an evaluation on memory models between DRAMSim3 and gem5, based on the current results I would suggest you use either DRAMSim3 (using the temporary solution I proposed) or

[gem5-users] Re: Problem with SimpleCache provided by learning_gem5/part2 when the ISA is ARM

Hi Fugelin, This is an interesting bug! I would guess that there's a packet being copied in the cache when it should be reused. The simple cache isn't tested with Arm, and it's really just an example and shouldn't be used for anything "real". If you do figure out the bug, we'd love to accept your

[gem5-users] Flushing the Caches

Hi, I was wondering if someone already implemented the functionality of flushing all caches in gem5. It seems relatively simple to implement and I imagine it would be useful in a lot of cases, yet I couldn't find anything online. Regards, Sherif ___