[gem5-users] Re: DRAM access rate too high?

2021-05-06 Thread Joardar, Biresh Kumar via gem5-users
Hi Wendy, I’m using the Gem5’s default open-adaptive page policy and the addresses belong to different rows. I also made sure that the same row is not being accessed consecutively. Following is the code I use to pick random address: const size_t mem_size = 1 << 28; char *g_mem; char *pick_addr()

[gem5-users] Re: DRAM access rate too high?

2021-05-06 Thread Wendy Elsasser via gem5-users
Hi Biresh, What is the page policy and what is the distribution across rows for your access pattern? For example, are these random addresses that should access different rows or is this sequential, in which case, the data will sequence across the column addresses within the same row. Thanks, We

[gem5-users] DRAM access rate too high?

2021-05-06 Thread Joardar, Biresh Kumar via gem5-users
Hello, I’m simulating a 4-core system connected to 1 DRAM bank. For this purpose, I set both the variables ‘ranks_per_channel’ and ‘banks_per_rank’ in the file src/mem/DRAMInterface.py to 1, and then recompile Gem5. Next, I run a single-thread test workload that has 95% cache miss rate and obser

[gem5-users] Committing loads

2021-05-06 Thread Farhad Yusufali via gem5-users
 Hello all, I’ve been staring at the memory trace of a benchmark and am confused as to why some loads that I expect to commit are not being committed. Note that I am using Ruby. I’ve been tracing the path loads take and it seems to be the following (More information can be found here https:/

[gem5-users] statistics on gem5

2021-05-06 Thread FARIDEH ZIAEE via gem5-users
Hi, thanks for your answer According to you ,should I use sim_second for computer performance? I need to compute performance by these equations: performance=1/execution time execution time=cpu clock cycles/clock rate cpu clock cycles =instruction count *CPI Can I use sim_second instead of e

[gem5-users] Re: gem5-users Digest, Vol 178, Issue 10

2021-05-06 Thread FARIDEH ZIAEE via gem5-users
Hi, thanks for your answer According to you ,should I use sim_second for computer performance? I need to compute performance by these equations: performance=1/execution time execution time=cpu clock cycles/clock rate cpu clock cycles =instruction count *CPI Can I use sim_second instead of e

[gem5-users] Re: Interface Message Buffers between the Network and the Ruby protocol

2021-05-06 Thread VEDIKA JITENDRA KULKARNI via gem5-users
Okay thanks a lot! I'll look into that. Vedika. Get Outlook for Android From: gabriel.busnot--- via gem5-users Sent: Thursday, May 6, 2021 3:35:40 PM To: gem5-users@gem5.org Cc: gabriel.bus...@arteris.com Subject: [gem5-users] Re: Inter

[gem5-users] Re: Interface Message Buffers between the Network and the Ruby protocol

2021-05-06 Thread gabriel.busnot--- via gem5-users
VEDIKA JITENDRA KULKARNI wrote: > Hi, thank you! So based on Dest NI it is decided that the packet is for > L1CACHE (0-15), > L2CACHE(16-31) or DIRECTORY (32-47), and vnet(0,1,2) decides which queue, > right? Correct. > I also wanted to know how the route.dest_ni is used? I didn't come across

[gem5-users] Re: statistics on gem5

2021-05-06 Thread Arthur Perais via gem5-users
On 5/6/21 10:47 AM, FARIDEH ZIAEE via gem5-users wrote: Hi, I have the following  questions  about simulation statistics: final_tick                 9724380737064 host_inst_rate        79246 host_mem_usage  1185244 host_op_rate         87406 host_seconds       68211.69 host_tick_rate    1292051

[gem5-users] Re: Interface Message Buffers between the Network and the Ruby protocol

2021-05-06 Thread VEDIKA JITENDRA KULKARNI via gem5-users
Hi, thank you! So based on Dest NI it is decided that the packet is for L1CACHE (0-15), L2CACHE(16-31) or DIRECTORY (32-47), and vnet(0,1,2) decides which queue, right? I also wanted to know how the route.dest_ni is used? I didn't come across code where dest_ni is used at the destination router.

[gem5-users] statistics on gem5

2021-05-06 Thread FARIDEH ZIAEE via gem5-users
Hi, I have the following questions about simulation statistics: final_tick 9724380737064 host_inst_rate79246 host_mem_usage 1185244 host_op_rate 87406 host_seconds 68211.69 host_tick_rate129205119 sim_freq 1 sim_insts54