[gem5-users] Re: Compiling failure for original code in gem5 book

2021-06-21 Thread Qishen Li via gem5-users
Hi Gabriel: 1. I change the file name from SConscript to hello (deregister simple_memobj), it could compile successfully. [LINK] -> X86/gem5.opt scons: done building targets. 2.I used the downloaded SConscript from the website. I'll show the content below. 3. I already added it into the so

[gem5-users] Re: Compiling failure for original code in gem5 book

2021-06-21 Thread Gabriel Busnot via gem5-users
It looks like you are not using the latest version of the tutorial source code. Where did you get the tutorial source code from? I would recommend checking out the tag v21.0.0.0 and starting from the code in src/learning_gem5/part2. gem5 API has recently changed and any file older than a couple o

[gem5-users] Re: Compiling failure for original code in gem5 book

2021-06-21 Thread Qishen Li via gem5-users
OK I’ll check it out. I got these code from gem5 book. By the way, could you give me the link for the latest tutorial guide and code so that I can follow them?(gem5 book’s code seems outdated) Thanks for the assistance! Gabriel Busnot via gem5-users 于2021年6月21日 周一09:46写道: > It looks like you are

[gem5-users] Re: Error with gem5 full system simulation

2021-06-21 Thread Thomas, Samuel via gem5-users
Hi Abhijeeth, With regards to your first message, it looks like you are using a custom configuration python script. Often times these errors occur from failing to import the objects in the same way based on the directory. For example, if you look at the script "configs/example/se.py" you'll see th

[gem5-users] Re: Write Buffer Configuration for Ruby

2021-06-21 Thread Gabriel Busnot via gem5-users
Hi Wang, If by "write buffer queue", you mean the "mandatoryQueue", then you cannot restrict its size wihtout risking an assert error as the sequencer does not check the mandatoryQueue fullness before enqueuing. Still, the maximum number of concurrent tag array and data array lookups can be co

[gem5-users] Re: Compiling failure for original code in gem5 book

2021-06-21 Thread Gabriel Busnot via gem5-users
If you follow each step carefully starting from here, you should be good ;) The tutorial has been updated recently to take the latest API changes into account. https://www.gem5.org/getting_started/ Gabriel ___ gem5-users mailing list -- gem5-users@gem5

[gem5-users] [Big, Little] clusters with CHI and SE mode

2021-06-21 Thread Javed Osmany via gem5-users
Hello I am trying to model a system such as 1) Initially there are two clusters, [big, little] a. Have studied fs_bigLITTLE.py to see how the different clusters are generated. 2) Make use of CHI 3) Run the system in SE mode. The command I am planning to use is the following

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

2021-06-21 Thread Gabriel Busnot via gem5-users
Hi Javed, I don't think that you want to use devices.CpuCluster as it is used to manage classic caches while you want to use Ruby caches. My first approach would be, using se.py as is: 1- Define two more options in CHI.py to specify the number of big (B) and the number of little (L) cpus fr

[gem5-users] Re: [Big, Little] clusters with CHI and SE mode

2021-06-21 Thread Javed Osmany via gem5-users
Many thanks for the pointers, Gabriel. Best Regards J.Osmany -Original Message- From: Gabriel Busnot via gem5-users [mailto:gem5-users@gem5.org] Sent: 21 June 2021 17:02 To: gem5-users@gem5.org Cc: Gabriel Busnot Subject: [gem5-users] Re: [Big, Little] clusters with CHI and SE mode

[gem5-users] Re: Queued Ports

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Sam, No, there's not good documentation on this (yet ;)). It's relatively easy to set up, though. Instead of using a single packet ptr, you can have a queue (or whatever datastructure you would like), and you can set the blocked flag only when it is "full" (e.g., the number of items in the stru

[gem5-users] Re: [gem5 version 20.1.0.5] Writing to satp in RISCV FS mode causes error when L1 caches are added.

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Deepak, Have you tried the latest gem5? There's been a lot of work in both gem5-21.0 and on gem5-develop to improve the RISC-V FS support. Another option would be to look at how the RISC-V code has changed to see if that helps diagnose this problem. Cheers, Jason On Fri, Jun 18, 2021 at 10:29

[gem5-users] Re: Making virtual address range of a PIO device uncacheable in x86 FS simulation.

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Deepak, Yeah, the cache disable bit may not work correctly in the page table walker/TLB. You can check the code there to see if that's what's going wrong. You can also try adding an E820 entry to the workload object (e.g., https://gem5.googlesource.com/public/gem5-resources/+/refs/heads/stable

[gem5-users] Re: Call m5ops writefile when simulation ends

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Pedro, No, I don't think there's an easy way to run m5_write_file on the guest from the host. That is an instruction that is executed on the guest, and the host can't easily control what is executing on the guest (especially when you consider that it has to execute in the right context, etc.).

[gem5-users] Re: Reserve a chuck of memory space in SE mode

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Xijing, You can set specific mappings from virtual to physical addresses by calling the `map()` function on the Process object from your python configuration file. See https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/sim/Process.py#37 Then, once you have a virtual->physical ma

[gem5-users] Re: Memory-Intensive C Programs in SE Mode

2021-06-21 Thread Jason Lowe-Power via gem5-users
Hi Sam, Are the (virtual, physical?) addresses different when you use the larger arrays? I wonder if the underlying mmap or malloc calls are breaking in SE mode somehow. Maybe, after you allocate in your guest code you can print out the virtual address to make sure it looks reasonable. You can als

[gem5-users] Read request and writebacks in gem5

2021-06-21 Thread Aritra Bagchi via gem5-users
Hi, Could anybody help me understand what happens in gem5 when a read request reaches a cache (say L3) and L2's write queue has a pending writeback (writeback that has not yet been written to L3) with the same block as the read request? Is the read request gets serviced from the write queue as the

[gem5-users] In-memory processor taking over the contents of host processor in SE mode

2021-06-21 Thread hissa alshamsi via gem5-users
Hello, I am using SE mode in gem5 and trying to implement the concept of processing in memory. I have added a TimingSimpleCPU in the memory configuration and trying to make it takeover all the contents of the host processor to be operated in the memory instead of the host CPU. I found out that

[gem5-users] HMC in SE mode using a single vault controller

2021-06-21 Thread hissa alshamsi via gem5-users
Hi everyone, I am trying to use HMC in SE mode. The problem is when I run hello world binary file or any other larger benchmark, apparently from stats.txt only one vault controller is being used. I don't know why the other controllers are shown to be in IDLE state with zero values. I have used