Hi Fengze,
No, there is no defined interface between different levels of the cache in
Ruby. Ruby is a "black box" in some sense, with input on the CPU side and
output on the memory side. See
https://www.gem5.org/documentation/learning_gem5/part3/MSIintro/ and
https://www.youtube.com/watch?v=XTIrVB
Hi
What is the interface between L1 and L2 cache in Ruby cache coherence model? Is
there a clear defined interface, similar to the icachePort and dcachePort
between CPU and memory, between different levels of caches in Ruby?
Thanks in advance
Fengze Yu ___