Hi Fengze,
No, there is no defined interface between different levels of the cache in
Ruby. Ruby is a "black box" in some sense, with input on the CPU side and
output on the memory side. See
https://www.gem5.org/documentation/learning_gem5/part3/MSIintro/ and
Hi
What is the interface between L1 and L2 cache in Ruby cache coherence model? Is
there a clear defined interface, similar to the icachePort and dcachePort
between CPU and memory, between different levels of caches in Ruby?
Thanks in advance
Fengze
Hi all,
I am using the gem5 version 21. I can find stats such as
*system.cpu.l2..overall_accesses::total* which indicates the
total number of L2 cache accesses of a specific type.
Could anyone tell what stats are in the stats.txt file for knowing a) the
number of responses reaches "membus" from