[gem5-users] Selecting and configuring a pre-fetcher

Dear gem5-ers -- I've been running an x86 DerivO3CPU pretty much as it comes, and now would like to configure it to correspond well to some reasonably recent Intel cpu. I noticed that the standard config includes no prefetcher. What would be a reasonable prefetched configuration to set up? What

[gem5-users] Re: Running SPEChpc 2021 benchmarks with gem5

Hi Chrysanthos, As indicated by this line, > ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(3,0) ]--- the problem seems to be that the root partition was identified incorrectly. You can run the `fdisk` command to find the location of the root partition. For exa

[gem5-users] Running SPEChpc 2021 benchmarks with gem5

Hello All, I would like to ask if it's possible to run SPEChpc 2021 benchmarks using gem5. I tried to run it with the x86-spec-cpu2017-benchmarks.py but I got the following error in the system.pc.com_1.device file: Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(3,0) CP

[gem5-users] Inconsistancy in insert and lookup of TLB

Hi all I am using X86 ISA to get the some statistics about TLB in FS mode. But when I was reading the code of TLB and pagetable-walker, I found an interesting thing. After serving page-walker for a miss, TLB is updated by Virtual Page Number (pagetable_walker,line517). However, when it wa

[gem5-users] Read main memory directly in the timing model

Hello everyone, I am new to the gem5 simulator. I would like to make a memory request to read data in the main memory only. In order to maintain coherence, I need to bypass the caches. How can I do that? The simulation should be in the timing model. Thank you for your help!