[gem5-users] Request for help, dirty bit setting, X86 page table walker

Dear All, I am trying to set the page table dirty bit Gem5 X86 *"pagetable_walker.cc" (*/src/arch/x86*),* but using below code in the *stepWalk* function , I am using TimingSimpleCPU. *if(!pte.d && mode == BaseMMU::Write){pte.d = 1; doWrite = true;}* But what I observed is

[gem5-users] Error when running test_bwd_bn test

Hi, When I run the DNNMark test_bwd_bn, docker run --rm -v ${PWD}:${PWD} -v ${PWD}/gem5/gem5-resources/src/gpu/DNNMark/cachefiles:/root/.cache/miopen/2.9.0 -w ${PWD} gcr.io/gem5-test/gcn-gpu:v21-2 gem5/build/GCN3_X86/gem5.opt gem5/configs/example/apu_se.py --num-compute-units 128 -n3 --gpu-to-

[gem5-users] How to Calculate The numCycles Value From stats.txt File Using The Other Reported Cycles

Hi, I have been adding the different reported cycles in the stats.txt file to see if they add up to the numCycles, but they do not. Is there a way to calculate the numCycles value shown in the stats.txt using the other cycles given in the stats.txt file for the O3? _

[gem5-users] Cacheline status throughout hierarchy

Hi all, I'm looking for a way to count the total number of dirty/clean blocks within the cache hierarchy to get an overall ratio from each cache simulated. So far I haven't had much luck in finding a straightforward way to do this other than running through the cache/base.cc file and manually look

[gem5-users] Re: Error when running test_bwd_bn test

Hi David, My guess is you are using gfx801 for this? If so, does the application actually error out at this point, or just proceed beyond it? If it's the latter, my guess is MIOpen is just complaining that you're running with an APU, which is less well optimized for. If it's the former, then