[gem5-users] Adding new X86 memory instruction for O3CPU

Hello everyone, I am new to gem5. I want to do some computing-in-memory experiments by adding new x86 memory instructions for O3CPU in gem5. Should I add pseudo instruction or real instruction for this work? And How can I add it? Thank you! ___ gem5-use

[gem5-users] Re: SPEC CPU2017 X86 SE mode - instruction 'palignr_Vdq_Wdq_Ib' unimplemented

On 3/13/2023 5:33 PM, Abitha Thyagarajan via gem5-users wrote: Hi Eliot and Mirco, I had the same issue with `palignr_Vdq_Wdq_Ib` being unimplemented. I tried compiling my application binary (i.e., the one I was trying to run on gem5, not gem5 itself) to exclude SSE which contains that instruc

[gem5-users] Re: gem5 / garnet / simple custom routing

When getting a segfault, you want to run the simulation in a debugger to know where it happens. Enabling the --with-asan --with-ubsan flags on scons can also help a lot when the segmentation fault occurs at a different place than the bug location in the code. Gabriel ___

[gem5-users] TLB Miss penalty in O3CPU and se.py

Hi, I’m currently simulating ARM O3CPU through SE mode. It was confirmed that generic page fault occurred and was restored in mmu. Does this process affect the entire cycle as a penalty? Regards, Haseung ___ gem5-users mailing list -- gem5-users@gem