On 5/2/2023 1:01 PM, Shen, Fangjia wrote:
Regarding the data latency, I think it depends on whether the cache is sequential access (access
cache tags, then data) or parallel access (access tags and data at the same time - common
optimization for the L1 cache). See the code for BaseCache::calcul
Regarding the data latency, I think it depends on whether the cache is
sequential access (access cache tags, then data) or parallel access (access
tags and data at the same time - common optimization for the L1 cache). See
the code for BaseCache::calculateAccessLatency. If sequentialAccess==tru
Dear gem5 community,
I try to simulate RISCV FS using the RISCVMatchedBoard but after 2
hours it does not get output in the terminal. Specifically, I use the
following command (with latest gem5 version): ./build/RISCV/gem5.opt
configs/example/gem5_library/riscvmatched-fs.py
To be noticed
Are you using the fs_bitLITTLE.py script?
Big/Little CPUs should be grouped under the bigCluster/littleCluster SimObjects.
This should be visible in both config.ini and in the stats file (e.g.)
[…]
system.bigCluster.clk_domain.clock500 #
Clock period in tick
