[gem5-users] Question on ARM-FS simulate on different bus protocol

2023-09-21 Thread Chunfeng Li via gem5-users
Hi everone: hope you are doing well I'm having some difficulties with full system emulation of ARM using gem5. My aim is to change the bus protocols in the ARM system to achieve higher transfer efficiency by linking different devices to different bus protocols. The machine model used is:

[gem5-users] Re: Simulation of Hybrid Memory in Gem5

2023-09-21 Thread Ayaz Akram via gem5-users
Hi Sadhana, In the screenshot you shared, the address ranges assigned to two memory devices are overlapping (0:1073741824 and 0:2147483648). You should modify the second range such that it does not start from 0 but starts from 1073741824 or some other address (such that the two ranges do not

[gem5-users] Re: Core Communication Latency

2023-09-21 Thread Mahyar Samani via gem5-users
Hello Kazi, If by core to core communication latency, you are referring to the latency imposed by read sharing a cache block, you can use TrafficGenerator from gem5 stdlib. The example below is most probably not the best way to do this, but I could successfully measure the latency of moving the

[gem5-users] Core Communication Latency

2023-09-21 Thread Kazi Asifuzzaman via gem5-users
Hi, I was wondering if there is a way to quantify the core to core communication latency with gem5? If so, can anyone please provide some guidelines to extract that information from simulation results? Thanks, Kazi ___ gem5-users mailing list --