Hi everone:
hope you are doing well
I'm having some difficulties with full system emulation of ARM using gem5.
My aim is to change the bus protocols in the ARM system to achieve higher
transfer efficiency by linking different devices to different bus
protocols. The machine model used is:
Hi Sadhana,
In the screenshot you shared, the address ranges assigned to two memory
devices are overlapping (0:1073741824 and 0:2147483648). You should modify
the second range such that it does not start from 0 but starts from
1073741824 or some other address (such that the two ranges do not
Hello Kazi,
If by core to core communication latency, you are referring to the latency
imposed by read sharing a cache block, you can use TrafficGenerator from
gem5 stdlib. The example below is most probably not the best way to do
this, but I could successfully measure the latency of moving the
Hi,
I was wondering if there is a way to quantify the core to core
communication latency with gem5? If so, can anyone please provide some
guidelines to extract that information from simulation results?
Thanks,
Kazi
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