Hi PaiJ,
Is the stats.txt file in m5out folder is empty? If yes, I think the root cause
is that gem5-tlm is using cxx_manager class to register each objects while the
registering of stat is missing.
My solution is adding a new method at CxxConfigManager::instantiate(bool
build_all){} . This
Hello all,
I have been working with gem5 for a while now. I'm trying to generate
statistics for the TLM example given in the
util/systemc/systemc_within_gem5/systemc_gem5_tlm example.
Since there were no in-built stats available for the sc_tlm_target.{cc,hh}, I
tried to create few of my own
Hi everyone, I would need to run a simulation of gem5 in Full System emulation
with RISCV architecture with a simple C program. I therefore tried to use the
--bare-metal option.
So, I tried to run the following command:
`./gem5/build/RISCV/gem5.opt ./gem5/configs/example/riscv/fs_linux.py
I analyzed a few debug log outputs.
The control flow varies here https://github.com/gem5/gem5/blob/stable/src/cpu/o3/commit.cc#L1172, when the instruction triggers the page fault in the TLB. Whether or not I remove this check for a fault in the commit step for my address, the instruction remains
