Hello everyone,
I am looking for a valid and working Fault Injector for gem5 with RISCV ISA for
Full System simulation, which supports transient and permanent faults.
Regarding the type of faults I have no stringent constraints, for sure I need
software level faults (register faults, memory et
CPU : Intel
OS: ubuntu-22
gem5: gem5-v23
After I pass the tutorial of **SETTING UP AND USING KVM ON YOUR MACHINE** and
that is to say that kvmCPU works in FS mode!\
\
But when I try to run an multithreaded program with openmp in se mode using
KVMCPU, it throw an error like this:
> src/cpu/kvm
Hi,
I am trying to access all entries of the page table in every tick inside
the cpu. Currently I am trying to access the page tabe externalize()
function by first accessing the thread context of a cpu core, then
getting the process pointer which holds a page table object.
All process pointe
Ah, I was trying to do this from arch/arm/process.cc, but I've found
sim/Process.py which seems to actually control what the value is (at least when
using the se.py config).
Turns out Process.py already sets a 64MB stack by default. This suggests GCC
crashing isn't due to running out of stack a
Hello,
I am looking at the AtomicSimpleCPU code in src/cpu/simple for x86 ISA. I
am trying to understand the following code snippet. Whenever this condition
is true for a given PC, it does NOT follow the regular fetch from the
instruction cache and then decode. This results in a macroop called
`Mi