Hi, just sharing some info I've found that look like a possible Gem5 bug:
Below around 1024 physical registers (for all three data types) memory usage is
at normal levels (around half a gb). At 1024 and beyond, memory usage reaches
incredibly high levels that even my machine with 500GB of
Hello, I plan to enable my program to read hardware information from the
underlying layer during full simulation, such as the hit rate of L1 cache, and
then schedule based on this information. However, I am not sure how to
implement it. My current idea is to add new instructions to Gem5 and
So in theory it should be possible, that the entry is accessed during the calculations and therefore cached, despite of being squashed shortly after?
Is there a difference whether an instruction is squashed because of a branch misspeculation or a page fault?
Gesendet: Mittwoch, 24. Januar
