So you are saying, it is not the address that the store instruction is supposed
to store the value, but rather the address of the instruction itself ? The
left-most boldface below:
0x41c0ec @_dl_debug_initialize+124: stlr x0, [x3] : MemWrite :
D=0x00492000 *A=0x498028
On 2/6/2024 11:13 AM, Nazmus Sakib via gem5-users wrote:
I think gem5 has this SplitDataRequest() method that breaks the request if it
would need more than one cacheline.
In fact, the page fault is occurring before it goes to the cache. The panic message says the address is 0x400. By
looking in
I think gem5 has this SplitDataRequest() method that breaks the request if it
would need more than one cacheline.
In fact, the page fault is occurring before it goes to the cache. The panic
message says the address is 0x400. By looking into the disassembly and the
output log of -debug-flag=ExecA
Greetings,
I am Geetansh from NSUT College, Delhi. I am doing a research on caches and
i am using gem5 for the experiments and benchmarking regarding the caches.
I tried going through the source code of the caches and tried making
changes as per my research which mainly focuses on caches line, tags
