Hi,
Is it possible to force x86 processor to run in Real Mode when simulating in SE
or Protected mode is the only possible configuration?
Thanks,
Alain
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Hi,
The gem5 ruby introduction page refers that both MESI 2-level and MESI
3-level as strictly-inclusive caches.
https://www.gem5.org/documentation/general_docs/ruby/
Is there any configurability in gem5 to change this behaviour to
non-inclusive or it requires to be done by protocol state machine