Re: [gem5-users] gem5-users Digest, Vol 138, Issue 18

Hi, having a error when reading a line of stats.txt, you can use the pdb debugging to find the wrong line > -原始邮件- > 发件人: gem5-users-requ...@gem5.org > 发送时间: 2018年1月24日 星期三 > 收件人: gem5-users@gem5.org > 抄送: > 主题: gem5-users Digest, Vol 138, Issue 18 > > Send gem5-users mailing list sub

[gem5-users] Assertion `!blk->isWritable()' failed

Hello all, I want to swap the sets[set] (the sets is SetType *sets ) which just visited with sets[0] I add the code at base_set_assoc,hh CacheBlk* accessBlock(Addr addr, bool is_secure, Cycles &lat) override { Addr tag = extractTag(addr); int set = extractSet(addr);

Re: [gem5-users] Re：sim_seconds is a huge different between x86-se mode and x86- fs mode ,under the same program condition

Hi Oscar, Thank you very much for your reply, it helps me a lot! Regards, lily 在2017-09-05 15:55:06,李莉写道： > Hi, > > > Then, I change my rcS file followed you said ， I get a new stats,txt > ,the sim_seconds is the actual simulation time for this program ,Am I >

[gem5-users] CPU will wait when happen the dtb miss ?

Hi all, CPU will wait when happen the dtb miss, when it is executing a program? Thanks in advance regards lily___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Re：sim_seconds is a huge different between x86-se mode and x86- fs mode ,under the same program condition

Hi Oscar. Thanks your rapid reply First of all ,you are right ,the fs mode commend line edit error, because of my careless Second , as you except ,the number of instructions executed is different. Then, I change my rcS file followed you said ， I get a new stats,txt ,the sim_seconds is the ac

[gem5-users] sim_seconds is a huge different between x86-se mode and x86- fs mode , under the same program condition

hello all, I emulate the same program in x86-se and x86-fs modes ,I have two puzzles when I get the stats.txt puzzle 1: the sim_seconds is huge different puzzle 2：the TLB accesses is huge different here is my program #include void main(){ int a [10240]; int i=0; int sum; for(i=0;i<=10239;

[gem5-users] Number of DTB write ≠Number of DTB write miss +number of DTB read miss

hello all， QUESTION 1: I check the information display that the number of DTB write number of = DTB write miss +number of DTB read miss But why gem5 statistics out of the data that the number of DTB write number of ≠ DTB write miss +number of DTB read miss This is my commend line in gem5

[gem5-users] x86/fs modify TLB hit latency and miss delay

dear all, I'm trying to modify the hit latency ,miss delay of TLB . I have read the source code about TLB for SimpleTimingCPU Two place confused me .First I can't find the latency about TLB hit lentency, is just one cycle for hit latency if it hit in the TLB ? or the gem5 ignore the hit latency.

[gem5-users] TLB translate time and miss delay

hello all， How can I get the TLB miss delay in fs x86 mode? Does gem5 simulate the TLB translate time ,i read the source code about x86/tlb.cc ,pagetableWalker.cc ,but i can't find the information about the time .does anyone have some idea? ___ gem5-u