Re: [gem5-users] RISCV nop executed as c.addi...

Nop is actually with the rd set to x0, and an immediate of 0 indicates an architectural hint, which gem5 doesn't have to my knowledge. That instruction appears to decode to c.addi x0, 0, which should do nothing even though it isn't explicitly decoded as a nop. What are you seeing happening? On T

Re: [gem5-users] Does Risc-V support multi-threaded applications in SE mode?

There has been work done on supporting multithreading with pthreads in SE mode and I believe it does work with RISC-V. If not, you can try these three patches: #16768 , #16769 ,

Re: [gem5-users] Remote gdb debug interface for RISCV/gem5.debug

ew and let me know. Thanks, Alec Roelke On Sat, Jul 20, 2019 at 2:12 PM Alec Roelke wrote: > Hi John, > > The GDB you're using should be fine. Your error is most likely a bug in > the GDB implementation in the RISC-V ISA within gem5. I can take a look at > it over the next w

Re: [gem5-users] RISC-V ISA + Gathering stats for ROI only

Hi Marcelo, You're right that RISC-V doesn't have m5_ops implemented yet, but one way you could get an instruction count is by reading the INSTRET CSR in your program just before your ROI, since that directly reads the CPU model's instruction counter. Hope this helps, Alec Roelke

Re: [gem5-users] RISC-V DerivO3CPU: Assertion `atomicOpFunctor != NULL' failed

or all of the commits. -Alec Roelke On Thu, Jul 18, 2019 at 1:15 PM Hossein Golestani wrote: > Forwarding a possible solution: > > > -- Forwarded message - > > Hi Hossein, > > I don't know if there is an update to this on you end, but here is how I >

Re: [gem5-users] Remote gdb debug interface for RISCV/gem5.debug

Hi John, The GDB you're using should be fine. Your error is most likely a bug in the GDB implementation in the RISC-V ISA within gem5. I can take a look at it over the next week or so, but if you find a fix for it yourself don't hesitate to submit a patch. -Alec Roelke On Wed, Jul 1

Re: [gem5-users] Get curTick at application level

Pseudo instructions haven't been implemented yet for RISC-V, so you're right in that you wouldn't be able to use them to do it. You could, however, implement a new CSR that tracks the current tick in a similar way to how the cycle CSR returns the clock cycle counter. If you look at src/arch/riscv

Re: [gem5-users] panic: Page table fault when accessing virtual address 0x8000000000000000

g me! > What is current status in the implementation RISC-V FS mode? > Also, what are the open issues and where are you tracking them? > For now, I will check the above files pointed by you. > > Thanks and Regards, > Rishabh Jain > > > > On Fri, Mar 8, 2019 at 8:17 PM

Re: [gem5-users] panic: Page table fault when accessing virtual address 0x8000000000000000

> contributing to gem5. > > Please let me know how to get started. > > Thanks and regards, > Rishabh Jain > > > > On Thu, Mar 7, 2019 at 8:19 AM Alec Roelke wrote: > >> When gem5 runs in SE mode, it is intended to mainly run user-level code, >> which highe

Re: [gem5-users] panic: Page table fault when accessing virtual address 0x8000000000000000

able hartID. But here, I am > using the csrr instruction, right? > As you mentioned earlier, may you please elaborate on reading CSRR > instruction? > > Thanks and Regards, > Rishabh Jain > > > > > > > > > On Mon, Mar 4, 2019 at 1:57 AM Alec Roelke wrote: >

Re: [gem5-users] panic: Page table fault when accessing virtual address 0x8000000000000000

Hi Rishabh, You're right that mhartid should not be the same for every CPU. It looks like you may have found a bug in RISC-V in that mhartid had not been implemented yet. This is odd, though, because I thought I had implemented it. In any case, try this patch ( https://gem5-review.googlesource.

Re: [gem5-users] Beginner script: "consecutive SC failures"

I had a chance to look into this, and the problem is that the data structure storing the sequence of locked reads is shared across all thread contexts, which means that if a thread context A locks an address and then B locks a different address, A has to unlock its address first, before B can, even

Re: [gem5-users] Beginner script: "consecutive SC failures"

Would you mind posting the exact command you used to run se.py? I should have some time in the next couple of days to look into this. Also, you may want to try applying this patch series, which changes the behavior of LR/SC and the AMO instructions to work better: https://gem5-review.googlesource

Re: [gem5-users] gem5-RISCV Assertion error while simulating 471.omnetpp

Are you using the latest version of gem5? That assert was replaced with a fault a while ago. On Thu, Sep 13, 2018 at 12:33 AM Gabe Black wrote: > This is a bug in the RISCV ISA. Either that instruction should have > decoded to something else if that group of bits was 0 (a different > instructio

Re: [gem5-users] RISCV ISA : "C" (compressed) extension supported?

Hi Marcelo, Yes, gem5 does support the C extension (64-bit version only, though). I don't know what could be causing your particular issue. I'm not sure advancePC is the issue, though, because all that essentially does is call PCState::advance(), which is inherited unchanged from GenericISA::UPC

Re: [gem5-users] pause while running on riscv

There's a bug with RISC-V that I haven't been able to work out yet where attempting to open a file that doesn't exist causes gem5 to hang rather than report failure. Make sure the file you're trying to open is actually where your program is looking for it. I find that this problem happens most of

Re: [gem5-users] Assertion error in RISCV isa

Great! I'm glad the patch works for you. Would you mind leaving a quick review for it? All you have to do is click "Reply," click the +1 next to Code-review, and maybe leave a little comment. On Sat, Mar 17, 2018 at 2:28 PM, Zaman, Monir wrote: > Quick update. > > Applied the patch and ran 44

Re: [gem5-users] Assertion error in RISCV isa

This is a bug with gem5; as Gabe pointed out, there shouldn't be asserts there. Patch #9261 was just uploaded and should fix this problem. Try applying it and let me know if the problem persists. The user-level specification says for th

Re: [gem5-users] m5ops with RISCV

g* this? > > Thanks a lot once again. > > V Vanchinathan > > On Wed, Dec 20, 2017 at 2:44 AM, Alec Roelke wrote: > >> Hi Vanchinathan, >> >> At the moment, there is not a patch for m5op support for RISC-V. If you >> want binaries to have access to performance

Re: [gem5-users] m5ops with RISCV

, CYCLE, and TIME do. -Alec Roelke On Tue, Dec 19, 2017 at 1:25 AM, Vanchinathan Venkataramani < dcsv...@gmail.com> wrote: > Dear all > > I would like to collect performance counters for a RISCV binary in gem5. > > Is there a util/m5 patch for generating m5ops for RISCV? Any help

Re: [gem5-users] RISCV port for gem5 [code works on spike not on gem5]

Hi Nitish, Yes, this is a bug with gem5, but I haven't been able to track down the problem myself. It could be due to some inaccuracy in setting up the program's memory (in src/arch/riscv/process.cc), which is based on my interpretation of the proxy kernel's code. -Alec Roelke

Re: [gem5-users] Error in the process of running SPEC CPU2006 Benchmarks in the gem5 Simulator

Hi Artemis, This problem is actually caused by an old version of gem5 that doesn't support RISC-V compressed instructions. I recently added a couple of patches to add support for the compressed ISA; try updating your copy of gem5 and run the benchmarks again. -Alec On Wed, Jul 19, 2017 at 8:58

Re: [gem5-users] Constant Defined but not Used

g debug checks (e.g., asserts) >> which are removed when compiling fast mode. To ignore these warnings from >> the compiler, there is the macro "M5_VAR_USED" which can be used after >> declaring the variable to make sure that it appears used to the compiler >> (like __a

[gem5-users] Constant Defined but not Used

rays in registers.hh work fine. This error only appears for some of the scalar constants. Is anyone else having this issue? Thanks, Alec Roelke ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] RISCV tool-chain commit point used for Gem5+RISCV

Hi Nitish, The latest release of gem5 supports binaries compiled with this commit of riscv-tools . There is a patch that adds support for the compressed ISA, #3860 (yo

Re: [gem5-users] RISC-V: TypeError and Unknown Instruction

I've never seen that first error before, but none of the code in that backtrace belongs to RISC-V. As for the second one, do you know which version of the toolchain you're using? Without the patch Jason linked you to, gem5 only supports this commit of riscv-tools

Re: [gem5-users] Link error building gem5.fast

;>>> are you using? >>>> >>>> Jason >>>> >>>> On Tue, May 23, 2017 at 3:41 PM Moussa, Ayman < >>>> ayman.mouss...@imperial.ac.uk> wrote: >>>> >>>>> Hey >>>>> >>>>> >>>>> I've encountered this exact p

[gem5-users] Link error building gem5.fast

t+0x5b00): multiple definition of `Drainable::drainResume()' build/X86/dev/x86/lib.fo.partial:(.text+0x0): first defined here There are way too many of these to list them all, but they're all multiple definitions of symbols. Has anyone else encountered this? T

Re: [gem5-users] Add instruction

://gem5.org/The_M5_ISA_description_language, which is also linked in the other page. -Alec Roelke On Mon, May 15, 2017 at 12:20 PM, Hossam Fouad wrote: > Hello , > i want to add new instruction (not pseudo instruction) to gem5 RISCV > architecture in order to test my code performance wit

[gem5-users] RISC-V Support

nks to everyone who reviewed the code and helped get it included into gem5! Regards, Alec Roelke ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] RISC-V ISA

er on the reviewers than posting one giant patch. For instance, you > can separate the required modifications to each CPU model into separate > patches. > > Thanks! > Jason > > On Mon, Sep 12, 2016 at 11:01 AM Alec Roelke wrote: > >> Thanks for your help everyone! I'm ac

Re: [gem5-users] RISC-V ISA

months and it had no functionality implemented. Mostly I copied from MIPS because RISC-V and MIPS have a lot of similarities. Also, if anyone plans to use this, please cite "RISC5: Implementing the RISC-V ISA in GEM5," which we plan to submit soon. Thanks, Alec Roelke On Fri, Sep 9, 2016

[gem5-users] RISC-V ISA

there? Thanks, Alec Roelke ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Micro-op Data Dependency

> where the other operands specify the machine code bitfield, if there's > syntax that allows that. > > Steve > > > On Tue, Aug 2, 2016 at 1:54 PM Alec Roelke wrote: > >> Okay, thanks. How do I tell the ISA parser that the 'Rt' operand I've >&g

Re: [gem5-users] Micro-op Data Dependency

, both >>> micro-ops should read that out of a register, it should not be passed >>> implicitly via hidden variables. >>> >>> You shouldn't have to explicitly set the internal fields like _srcRegIdx >>> and _destRegIdx, the ISA parser should do that fo

Re: [gem5-users] Micro-op Data Dependency

ve to explicitly set the internal fields like _srcRegIdx > and _destRegIdx, the ISA parser should do that for you. > > Unfortunately the ISA description system wasn't originally designed to > support microcode, and that support was kind of shoehorned in after the > fact, so it i

Re: [gem5-users] Micro-op Data Dependency

rhaps if you show some snippets of your actual code it will be clearer > to me what's going on. > > Steve > > > On Fri, Jul 29, 2016 at 9:33 AM Alec Roelke wrote: > >> Yes, that sums up my issues. I haven't gotten to tackling the second one >> yet; I'm

Re: [gem5-users] Micro-op Data Dependency

/microops/ldstop.isa). This works with AtomicSimpleCPU > and with Ruby, but there is no support for enforcing this atomicity in the > classic cache in timing mode. I have a patch that provides this but you > have to apply it manually: http://reviews.gem5.org/r/2691. > > Steve >

[gem5-users] Micro-op Data Dependency

data dependency between the two micro-ops in the instruction? Or, better yet, is there a way I could somehow have two memory accesses in one instruction without having to split it into micro-ops? Thanks, Alec Roelke ___ gem5-users mailing list gem5-users@gem

[gem5-users] 4-Way SMT

Hello Everyone, I’m trying to run SPARC simulations with multithreaded programs on a single core. I’ve increased the number of integer registers per core to fit all the threads they need to run and get past the numPhysIntRegs >= numThreads*TheISA::NumIntRegs assertion, and I can get benchmarks

[gem5-users] (no subject)

Hello, I’m trying to simulate a SPARC processor with SMT enabled in SE mode. When I enable the SMT switch (using --smt --cpu-type=detailed --caches) with a single core, it works fine if there’s only one workload. If I add a second workload, though, I get an assertion error that “params->numPh