[gem5-users] Re: In Ruby, I have changed my MESI_Three_Level-L0cache.sm, but panic: Runtime error, assert failure

Hello Zhen, Icache is the reference to the L0-instructions cache and Dcache is the one to the L0-data cache. It's usual to find the first level of a conventional cache hierarchy split into instructions and data. The purpose of the assert is, basically, to check that the same block is not pr

[gem5-users] [ARM O3 SE] Panic: Page table fault

Hi all, Since executing workloads compiled for arm-32-bits is giving me problems (https://gem5.atlassian.net/browse/GEM5-438), I compiled them for AArch64. However, for some of the workloads (SPEC CPU 2006) I'm encountering a page table fault. Has anyone already dealt with this issue? (Givin

[gem5-users] Assertion failing for SE mode for O3 cpu ARM

Hi all, I'm encountering the assertion fail reported herehttps://gem5.atlassian.net/browse/GEM5-438. I'm trying to execute SPEC CPU 2006 in SE mode for O3 cpu. I'm doing fast forward and I'm getting the assertion fail at the switching cpu. As I

[gem5-users] Re: [SE Multicore Ruby] Assertion failed for multicore simulation

Hi Taiyu, Jason, As far as I could go through it I end up thinking that something is crashing during a syscall: The crash is related to unfound input files of the benchmark/application you are running over the 'se'. Therefore, what I did is to double check the input/output data files the be

[gem5-users] Re: GEM5/Ruby and MESI_Three_Level protocol

Hello, Open the file 'MESI_Three_Level.slicc' and you will see the files the protocol MESI_Three_Level is being generated from. You will see that it is using some components from the MESI_Two_Level protocol. Hope this is helping you. Carlos On 28/5/20 11:48, Javed Osmany via gem5-users