[gem5-users] hyperthreading on gem5 full-system using DeriveO3CPU

Hi all, Is it possible to do hyperthreading on a gem5 FS simulation? I am using DerivO3CPUs, and hyperthreaded applications seem to run, but the threads seem to be running sequentially on each CPU (as in one thread runs to completion before starting the next), rather than running in a hyperthreade

[gem5-users] difference between DerivO3CPU and O3_ARM_v7a

Hi all, This is a high level question, but what's the difference between DerivO3CPU and O3_ARM_v7a? Is it the level of detail? Thanks, Jiwon ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(w

[gem5-users] Re: 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

> We recently uploaded a prebuilt Ubuntu18.04 on gem5.org: > > > http://dist.gem5.org/dist/current/arm/disks/ubuntu-18.04-arm64-docker.img.bz2 > > Kind Regards > > Giacomo > > > -Original Message- > > From: Choe, Jiwon via gem5-users > > Sent: 2

[gem5-users] Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27

Hi all, I'm looking for a Linux disk image for 64-bit ARM that has GLIBC version 2.27 (Ubuntu 18.04+ I think). I am trying to run Java JDK that has been compiled on Ubuntu 18.04 (with GLIBC 2.27) on a gem5 ARM FS simulation. I am currently using the disk image that I got from here: http://dist.ge

[gem5-users] ARM full-system simulation error during checkpoint: rcu_preempt detected stalls on CPUs/tasks

Hi, I am currently running a 32-bit ARM full-system simulation. After I boot up the OS on the simulated system, I take a checkpoint. This worked fine before, but after I made some changes to the DRAM controller code, the checkpoint stalls and I get this error message in the simulated console: IN

[gem5-users] heterogeneous core configuration and mapping threads in gem5 FS simulation

Hi all, I was wondering if the following would be possible with a gem5 full-system simulation, and I thought this would be the best place to ask. I want to simulate a multicore system with two different configurations of cores coexisting in the same system. One set of the cores (I'll call this A-

[gem5-users] increasing disk image size for full system simulation

Hi all, This might not be exactly gem5-related, but I was wondering if anyone on this mailing list has done this before and could help me out. I'm trying to increase the .img disk image size, and I thought I had made some progress by using "qemu-img resize" and "parted" linux commands. But when I

[gem5-users] drampower meaning of background energy

Hi, I am looking into the stats from drampower, and I am confused on what "activation background energy" and "precharge background energy" stats refer to. Are these simply leakage energy? Why is there a distinction between "activation" background energy and "precharge" background energy? Thanks,

Re: [gem5-users] Reducing main memory size in full-system simulation

ine? > > How does the simulation shuts down? The kernel kills the guest program? > Do you get a message? How did you check that the guest program simply > didn't run out of memory? > > > On Thu, Jun 28, 2018 at 6:14 PM, Choe, Jiwon wrote: > >> I am running a

[gem5-users] Reducing main memory size in full-system simulation

I am running a Linux ARM full-system simulation, and I have been having problems after reducing the main memory size from 512 MB to 256 MB. After reducing the memory size, the simulation works fine up to booting the OS. However, when I try to run my application on the simulated system (via a .rcs

[gem5-users] L1 dcache misses with full-system simulation

Hi, I am running some multicore, multithreaded benchmarks (1 thread/core) on a gem5 full-system simulation, and I am having trouble interpreting the data cache misses that I am seeing. As far as I am concerned, the threads do not share any data. However, I am seeing an increase in data cache miss

[gem5-users] concurrent read/writes to memory in gem5 full-system simulation

Hi, I currently have a full-system simulation set up with multiple simple timing processors, each with private icache and dcache, and a shared L2 cache. On this simulator, I have been running some multithreaded benchmarks that have concurrent read/writes to memory. On a typical real system, these