[gem5-users] TLM Bridge Compilation Issues

Hi All, I am on the latest commit on master (9fc9c67b4242c03f165951775be5cd0812f2a705) and trying to follow along the steps provided in util/TLM/README. However, I am seeing some compilation errors when executing this command: scons --with-cxx-config --without-python --without-tcmalloc build/AR

[gem5-users] Instruction Class Latencies

Hi all, I am aware that we can set latencies on an opClass basis (ex. MemRead) for the O3_ARM_v7a CPU, but is it possible to set instruction-specific (ex. LDREX) latencies? Thanks, Paul ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/

[gem5-users] Cache Latency Calculation

Hi, I am investigating the cache latencies of different CPU models (HPI and O3_ARM_v7a) and trying to understand how the latencies for memory access are calculated. I have come up with a preliminary formula through experimentation for the O3_ARM_v7a model: Total latency for L1 Hit = Memory OpL