[gem5-users] Registering TLB to System.l2 prefetcher

Hi, I am looking for some help to enable the TLB for the system.l2 prefetcher. I see that we can register the TLB for dcache and icache by modifying the CacheConfig.py as below. icache.prefetcher = hwpClass() icache.registerTLB(system.cpu[i].itb) dcache.prefetcher = hwpClass() dcache.r

[gem5-users] Page crossing prefetch

Hi, Has anyone looked at enabling page crossing prefetch in Gem5? I see the below code where it says ignoring the page crossing prefetch if the new address is not in the same page. } else { DPRINTF(HWPrefetch, "Ignoring page crossing prefetch.\n"); } Thanks, Rejith