I believe: https://gem5-review.googlesource.com/c/public/gem5/+/17541
creates a merge conflict when removing the above commit.
So: I had to remove both commits.
Thanks Ryan.
On Tue, Mar 26, 2019 at 1:13 AM Rishabh Jain wrote:
> Yesss! It worked :)
>
> On Mon, Mar 25, 2019 at 10:17 A
/configs/common/Options.py#b44
>
> Ryan Gambord
>
>
> On Sat, Mar 23, 2019 at 9:40 PM Rishabh Jain
> wrote:
>
>>
>> Hi Jason,
>>
>> Even though I remove the ' . ' before Benchmarks at line 48 in
>> "configs/common/Options.py", I still get erro
gt; However, it seems surprising that this hasn't been caught before. Are you
> using Python 2.7?
>
> Jason
>
> On Tue, Mar 19, 2019 at 10:33 AM Rishabh Jain
> wrote:
>
>> I forgot to add the network flag:
>> $ ./build/NULL/gem5.debug configs/example/garnet_synth_tr
will have to target them and do some calculations.
I am struggling with how these variables are defined and where are they
defined.
Am I missing something?
Can somebody give me pointers on how to make progress in getting the Packet
Trace?
Best,
Rishabh Jain
I forgot to add the network flag:
$ ./build/NULL/gem5.debug configs/example/garnet_synth_traffic.py
--network=garnet2.0 --topology=Mesh_XY --num-cpus=16 --num-dirs=16
--mesh-rows=4
But still the same *ValueError* persists.
On Tue, Mar 19, 2019 at 10:50 PM Rishabh Jain wrote:
> Hello every
ed relative import in non-package
*
But, when I use the mercurial repository of gem5 (I know its outdated), the
above command works just fine.
Can somebody help me in debugging the error?
Best,
Rishabh Jain
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etPtr,
unsigned int): Assertion `!pkt->isWrite()' failed."
Am I missing something?
On Tue, Mar 19, 2019 at 4:50 PM Rishabh Jain wrote:
> Hello everyone,
>
> I am getting an error while running "simple.py" configuration file,
> present at configs/learning_gem5/part1/ when
"build/RISCV/mem/dram_ctrl.cc" fails.
Can somebody help in fixing this issue?
Best,
Rishabh Jain
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Hi Alec,
Thanks for welcoming me!
What is current status in the implementation RISC-V FS mode?
Also, what are the open issues and where are you tracking them?
For now, I will check the above files pointed by you.
Thanks and Regards,
Rishabh Jain
On Fri, Mar 8, 2019 at 8:17 PM Alec Roelke
to implement RISC-V FS mode? If yes, I wish to help by
contributing to gem5.
Please let me know how to get started.
Thanks and regards,
Rishabh Jain
On Thu, Mar 7, 2019 at 8:19 AM Alec Roelke wrote:
> When gem5 runs in SE mode, it is intended to mainly run user-level code,
> which higher-pri
truction, right?
As you mentioned earlier, may you please elaborate on reading CSRR
instruction?
Thanks and Regards,
Rishabh Jain
On Mon, Mar 4, 2019 at 1:57 AM Alec Roelke wrote:
> Hi Rishabh,
>
> You're right that mhartid should not be the same for every CPU. It looks
> like y
/pastebin.com/0xNyGkCE
Also, my max_miss_count parameter in config.ini remains to be 0 for all
caches.
I am unable to understand this error?
Other than this, may someone guide me to the steps of finding memory trace
and instruction trace for a binary executed on gem5 in RISC-V isa.
Thanks and regards,
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