[gem5-users] Re: DRAM access rate too high?

Hi Biresh, What is the page policy and what is the distribution across rows for your access pattern? For example, are these random addresses that should access different rows or is this sequential, in which case, the data will sequence across the column addresses within the same row. Thanks, We

[gem5-users] Re: Infinite loop in memory controller

Hi Taiyu, Looks like you have a single memory controller with 2 ranks instantiated. * The log flags labeled system.mem_ctrls are for general controller messages * The log flags labeled system.mem_ctrls_0 relate to rank 0 specific info * The log flags labeled system.mem_ctrls_1 relate t

[gem5-users] Re: a problem about memory access latency of HMC

Hi, Yes, more info would be helpful. I would specifically look for log messages regarding refresh and self-refresh operations. Those are some conditions that would put the controller / memory in a busy state. The READ command would be delayed until either the refresh completes or a self-refresh