Re: [gem5-users] classic memory system protocol specification

2015-07-15 Thread cao2
This is my flow graph, the one I send before was too big. Best, Yuting > On Jul 14, 2015, at 2:05 PM, cao2 wrote: > > Hi there > > I'm doing research about verifying the correctness of protocol communication > between each component. The criterial I use to judge

Re: [gem5-users] classic memory system protocol specification

2015-07-15 Thread cao2
> On Jul 14, 2015, at 2:05 PM, cao2 wrote: > > Hi there > > I'm doing research about verifying the correctness of protocol communication > between each component. The criterial I use to judge is the specification of > the protocol. What I have right now is found on

[gem5-users] classic memory system protocol specification

2015-07-14 Thread cao2
Hi there I'm doing research about verifying the correctness of protocol communication between each component. The criterial I use to judge is the specification of the protocol. What I have right now is found on gem5 wikipage, I did some modification according to the tracing result I have, but I

[gem5-users] SystemXBar latency

2015-07-08 Thread cao2
HI there I notice that the tick displayed membus receiving function and sending function are the same, is there any way I can add a latency in between for better tracing result? Regards, Yuting ___ gem5-users mailing list gem5-users@gem5.org http://m5

[gem5-users] SE mode protocol

2015-07-04 Thread cao2
Hi there I'm trying to run the se mode with moesi_cmp_directory protocol, I did it by run "scons build/ARM/gem5.opt protocol=moesi_cmp_directory". and the command I used to run the simulation is : build/ARM/gem5.opt configs/example/se.py --cpu-type=timing -n 2 --caches --mem-size=1GB --l1d_si

[gem5-users] Classic memory mode cache communication

2015-07-04 Thread cao2
Hi there I have a platform with two cpu with its own icache and dcache and one classic memory. When I added CommMonitor between all the ports and try to trace the message communication, I notice that when the cpu send a timing request to data cache, the instruction cache will instead send a tim

Re: [gem5-users] SE mode Peripherals

2015-06-28 Thread cao2
ect it with the > standard gem5 memory-system ports, then use memory-mapped I/O to access it. > The thing with a USB drive is that you will need a USB hub to talk to it, you > can't plug a USB device directly into the memory system. > > Steve > > On Sun, Jun 28, 201

Re: [gem5-users] SE mode Peripherals

2015-06-28 Thread cao2
(see > src/sim/Process.py) to map the device registers into your program address > space, but from there it's up to you to do the proper MMIO accesses to get it > to work. > > Steve > > > On Fri, Jun 26, 2015 at 12:47 PM cao2 <mailto:c...@mail.usf.edu>>

[gem5-users] SE mode Peripherals

2015-06-26 Thread cao2
Hi Can SE mode have peripherals like terminal, usb or anything? I can't seem to find any related documentation. Best, Cao ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Print packet information

2015-06-23 Thread cao2
Hi there I'm trying to use CmmMonitor to print sender of the packet and the packet command, can anyone give me some examples of changing commMonitor to print what I want? Best, Cao ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-