Hi all : I need to construct a MPSoC system based on Gem5 FS mode. And I have chosen the Ruby Garnet Network with MESI_Three_Level protocol as the interconnect bus. Now I would like to add some pio devices into the network.
In general, I expect cpu cores and devices can communicate with each other through the Garnet network. So I think I can't add the devices into the realview io device/mem system accessed by the iobus. I should add the device to attach the Directory Controller. But I also expect the devices don't participate in the cache coherence protocol. So, I sincerely hope to get some help about how to make L0-L2 Cache Controller and Directory Controller bypass the access request to the devices. Of course, welcome to give me some better ideas to fulfill my needs. Thanks and regards, Lee. _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
